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rx64m group renesas mcus preliminary datasheet specifications in this document are tentative and subject to change. r01ds0173ej0090 rev.0.90 page 1 of 67 feb 28, 2014 features 32-bit rxv2 cpu core ? max. operating frequency: 120 mhz capable of 240 dmips in operation at 120 mhz ? single precision 32-bit ieee-754 floating point ? two types of multiply-and-accumula tion unit (between memories and between registers) ? 32-bit multiplier (fastest instruction execution takes one cpu clock cycle) ? divider (fastest instruction execution takes two cpu clock cycles) ? fast interrupt ? cisc harvard architecture with 5-stage pipeline ? variable-length instructions: ultra-compact code ? supports the memory protection unit (mpu) ? jtag and fine (two-line) debugging interfaces low-power design and architecture ? operation from a single 2.7- to 3.6-v supply ? low power consumption: a product that supports all peripheral functions draws only 0.3ma/mhz (typ.). ? rtc is capable of operation from a dedicated power supply. ? four low-power modes on-chip code flash memory, no wait states ? supports versions with up to 4 mbytes of rom ? 120-mhz operation, 8.3-ns read cycle (no wait states) ? user code is programmable by on -board or off-board programming. ? programming/erasing as background operations (bgos) on-chip data flash memory ? max. 64 kbytes, reprogrammable up to 100,000 times ? programming/erasing as background operations (bgos) on-chip sram ? 512 kbytes of sram (no wait states) ? 32 kbytes of ram with ecc (one wait state, single-error correction and double error detection) ? 8 kbytes of standby ram (backup on deep software standby) data transfer ? dmac: 8 channels ? dtc ? exdmac: 2 channels ? dmac for the ethernet controller: 2 channels for 176- and 177-pin products; 1 channel for 100-, 144-, and 145-pin products reset and supply management ? power-on reset (por) ? low voltage detection (lvd) with voltage settings clock functions ? external crystal oscillator or internal pll for operation at 8 to 24 mhz ? internal 240-khz loco and hoco selectable from 16, 18, and 20 mhz ? 120-khz clock for the iwdta real-time clock ? adjustment functions (30 seconds, leap year, and error) ? real-time clock counting and binary counting modes are selectable ? time capture function (for capturing times in response to event-signal input) independent watchdog timer ? 120-khz (1/2 loco frequency) clock operation useful functions for iec60730 compliance ? oscillation-stoppage detection, frequency measurement, crc, iwdta, self-diagnostic functio n for the a/d converter, etc. ? register write protection function can protect values in important registers against overwriting. various communications interfaces ? ethernet mac (for 176- and 177-pin products: 2 modules) ? phy layer for host/function or ot g controller (1) with full-speed usb 2.0 with battery charging transfer (only for 176- and 177-pin products) ? phy layer (1) for host/function or otg controller (1) with full- speed usb 2.0 transfer ? can (compliant with iso11898-1), incorporating 32 mailboxes (up to 3 modules) ? scig and scih with multiple functionalities (up to 9) choose from among asynchronous mode, clock-synchronous mode, smart-card interface mode, si mplified spi, simplified i 2 c, and extended serial mode. ? scifa with 16-byte transmission and reception fifos (up to 4 interfaces) ? i 2 c bus interface for transfer at at up to 1 mbps (up to 2 interfaces) ? four-wire qspi (1 interface) in addition to rspia (1 interface) ? parallel data capture unit (pdc) fo r the cmos camera interface (not in 100-pin products) ? sd host interface (optional: 1 interface) with a 1- or 4-bit sd bus for use with sd memory or sdio external address space ? buses for full-speed data transfer (max. operating frequency of 60 mhz) ? 8 cs areas ? 8-, 16-, or 32-bit bus space is selectable per area ? independent sdram area (128 mbytes) up to 29 extended-function timers ? 16-bit tpua, mtu3a, and gpta: input capture, output compare, pwm waveform output ? 8-bit tmra (4 channels), 16-bit cm t (4 channels), 32-bit cmtw (2 channels) 12-bit a/d converter ? two 12-bit units (8 channels fo r unit 0; 21 channels for unit 1) ? self diagnosis ? detection of analog input disconnection 12-bit d/a converter: 2 channels ? on-chip operational amplifier output or direct input selectable temperature sensor for measuring temperature within the chip encryption (optional) ? aes (key lengths: 128, 196, and 256 bits) ? des (key lengths: 56 bits (d es); 3 56 bits (t-des)) ? sha (sha-1 (128), sha-2 (224 or 256), hmac (160, 224, or 256)) up to 127 pins for general i/o ports ? 5-v tolerance, open drain, input pull-up, switchable driving ability operating temp. range ? ?40 ? c to +85 ? c plqp0176kb-a 24 24 mm, 0.5-mm pitch plqp0144ka-a 20 20 mm, 0.5-mm pitch plqp0100kb-a 14 14 mm, 0.5-mm pitch ptlg0177ka-a 8 8 mm, 0.5-mm pitch ptlg0145ka-a 7 7 mm, 0.5-mm pitch ptlg0100ja-a 7 7 mm, 0.65-mm pitch plbg0176ga-a 13 13mm, 0.8-mm pitch 120-mhz 32-bit rx mcu, on-chip fpu, 240 dmips, up to 4-mb flash memory, 512-kb sram, various communications interfaces including ieee 1588-compliant ethernet mac, full-speed usb 2.0 with battery charging, sd host interface (optional), quad spi, and can, 12-bit a/d converter, rtc, encryption (optional), serial interface for audio, cmos camera interface r01ds0173ej0090 rev.0.90 feb 28, 2014 features
rx64m group 1. overview under development preliminary document specifications in this document are tentative and subject to change. r01ds0173ej0090 rev.0.90 page 2 of 67 feb 28, 2014 1. overview 1.1 outline of specifications table 1.1 lists the specifications in outline, and table 1.2 gives a comparison of the functions of products in different packages. table 1.1 shows the outline of maximum specifications, and th e number of peripheral module channels differs depending on the pin number on the package and th e code flash memory cap acity. for details, see table 1.2, comparison of functions for different packages . table 1.1 outline of specifications (1/9) classification module/function description cpu cpu ? maximum operating frequency: 120 mhz ? 32-bit rx cpu (rx v2) ? minimum instruction execution time: one inst ruction per state (cycle of the system clock) ? address space: 4-gbyte linear ? register set of the cpu general purpose: sixteen 32-bit registers control: ten 32-bit registers accumulator: two 72-bit registers ? basic instructions: 75 ? floating-point instructions: 11 ? dsp instructions: 23 ? addressing modes: 10 ? data arrangement instructions: little endian data: selectable as little endian or big endian ? on-chip 32-bit multiplier: 32 32 64 bits ? on-chip divider: 32 / 32 32 bits ? barrel shifter: 32 bits fpu ? single precision (32- bit) floating point ? data types and floating-point exceptions in conformance with the ieee754 standard memory flash memory (code flash) ? capacity: 2 mbytes, 2.5 mbytes, 3 mbytes, 4 mbytes ? 120 mhz, no-wait access ? on-board programming: four types ? off-board programming (parallel programmer mode) e2 data flash ? capacity: 64 kbytes ? programming/erasing: 100,000 times ram ? capacity: 512 kbytes ? 120 mhz, no-wait access ram with ecc ? capacity: 32 kbytes ? 120 mhz, single wait access ? sec-ded (single error correction/double error detection) standby ram ? capacity: 8 kbytes ? operation synchronized with pclkb: up to 60 mhz, two-cycle access operating modes ? operating modes by the mode-setting pins single-chip mode boot mode (for the sci interface) boot mode (for the usb interface) user boot mode ? operating modes by register setting single-chip mode, user boot mode on-chip rom disabled extended mode on-chip rom enabled extended mode ? endian selectable
rx64m group 1. overview under development preliminary document specifications in this document are tentative and subject to change. r01ds0173ej0090 rev.0.90 page 3 of 67 feb 28, 2014 clock clock generation circuit ? main clock oscillator, sub clock oscillator, low-speed/high-speed on-chip oscillator, pll frequency synthesizer, and iwdt- dedicated on-chip oscillator ? main-clock oscillation stoppage detection ? separate frequency-division and multiplication settings for the system clock (iclk), peripheral module clock (pclka, pclkb, pclkc, pclkd), flash-if clock (fclk) and external bus clock (bclk) the cpu and other bus masters run in sync hronization with the system clock (iclk): up to 120 mhz peripheral modules of mtu3, gpt, rspi, scifa, usba, etherc, eptpc, edmac, and aes run in synchronization with pclka, which operates at up to 120 mhz. other peripheral modules run in synchr onization with pclkb: up to 60 mhz adclk in the sd12ad (unit 0) runs in synchronization with pclkc: up to 60 mhz adclk in the sd12ad (unit 1) runs in synchronization with pclkd: up to 60 mhz flash if run in synchronization with t he flash-if clock (fclk): up to 60 mhz devices connected to the external bus run in synchronization with the external bus clock (bclk): up to 60 mhz ? multiplication is possible with using the hi gh-speed on-chip oscillator (hoco) as a reference clock of the pll circuit reset nine types of reset ? res# pin reset: generated when the res# pin is driven low. ? power-on reset: generated when the res# pin is driven high and vcc = avcc0 = avcc1 rises. ? voltage-monitoring 0 reset: generated when vcc = avcc0 = avcc1 falls. ? voltage-monitoring 1 reset: generated when vcc = avcc0 = avcc1 falls. ? voltage-monitoring 2 reset: generated when vcc = avcc0 = avcc1 falls. ? deep software standby reset: cancels deep software standby mode by an interrupt. ? independent watchdog timer reset: generated when the independent watchdog timer underflows, or a refresh error occurs. ? watchdog timer reset: generated when the watchdog timer underflows, or a refresh error occurs. ? software reset: generated by register setting. power-on reset if the res# pin is at the high level when power is supplied, an internal reset is generated. after vcc = avcc0 = avcc1 has exceeded the voltage detection level and the specified period has elapsed, the reset is cancelled. voltage detection circuit (lvda) monitors the voltage being i nput to the vcc = avcc0 = avcc1 pins and generates an internal reset or internal interrupt. ? voltage detection circuit 0 capable of generating an internal reset the option-setting memory can be used to select enabling or disabling of the reset. voltage detection level: selectable from three different levels (2.94 v, 2.87 v, and 2.80 v) ? voltage detection circuits 1 and 2 voltage detection level: selectable from three different levels (2.99 v, 2.92 v, and 2.85 v) digital filtering (1/2, 1/4, 1/8, and 1/16 loco frequency) capable of generating an internal reset ? two types of timing are selectable for release from reset an internal interrupt can be requested. ? detection of voltage rising above and falling below thresholds is selectable. ? maskable or non-maskable interrupt is selectable voltage detection monitoring event linking low power consumption low power consumption facilities ? module stop function ? four low power consumption modes sleep mode, all-module clock stop mode, software standby mode, and deep software standby mode battery backup function ? when the voltage on the vcc pin drops, battery power from the vbatt pin is supplied to keep the real-time clock operating. table 1.1 outline of specifications (2/9) classification module/function description
rx64m group 1. overview under development preliminary document specifications in this document are tentative and subject to change. r01ds0173ej0090 rev.0.90 page 4 of 67 feb 28, 2014 interrupt interrupt controller (icua) ? peripheral function interrupts: 293 sources ? external interrupts: 16 (pins irq0 to irq15) ? software interrupts: 2 sources ? non-maskable interrupts: 7 sources ? sixteen levels specifiable for the order of priority ? method of interrupt source selection: the interrupt vectors consist of 256 vector s (128 sources are fixed. the remaining 128 vectors are selected from among the other 156 sources.) external bus extension ? the external address space can be divided into eight areas (cs0 to cs7), each with independent control of access settings. capacity of each area: 16 mbytes (cs0 to cs7) a chip-select signal (cs0# to cs7#) can be output for each area. each area is specifiable as an 8-, 16-, or 32-bit bus space. the data arrangement in each area is select able as little or big endian (only for data). ? sdram interface connectable ? bus format: separate bus, multiplex bus ? wait control ? write buffer facility dma dma controller (dmacaa) ? 8 channels ? three transfer modes: normal transfer, repeat transfer, and block transfer ? activation sources: software trigger, exter nal interrupts, and interrupt requests from peripheral functions exdma controller (exdmaca) ? 2 channels four transfer modes: normal transfer, r epeat transfer, block transfer, and cluster transfer ? single-address transfer enabled with the edackn signal ? activation sources: software trigger, exte rnal dma requests (edreqn), and interrupt requests from peripheral functions data transfer controller (dtca) ? three transfer modes: normal transfer, repeat transfer, and block transfer ? activation sources: external interrupts and interrupt requests from peripheral functions i/o ports programmable i/o ports ? i/o ports for the 177-pin tflga (in planni ng), 176-pin lfbga (in planning), and 176-pin lqfp i/o pins: 127 input pin: 1 pull-up resistors: 127 open-drain outputs: 127 5-v tolerance: 19 ? i/o ports for the 145-pin tflga (in planning) and 144-pin lqfp i/o pins: 111 input pin: 1 pull-up resistors: 111 open-drain outputs: 111 5-v tolerance: 18 ? i/o ports for the 100-pin tflga (in planning) and 100-pin lqfp i/o pins: 78 input pin: 1 pull-up resistors: 78 open-drain outputs: 78 5-v tolerance: 17 event link controller (elc) ? event signals such as interrupt request signals can be interlinked with the operation of functions such as timer count ing, eliminating the need for intervention by the cpu to control the functions. ? 119 internal event signals can be freely combined for interlinked operation with connected functions. ? event signals from peripheral modules can be used to change the states of output pins (of ports b and e). ? c hanges in the states of pins (of por ts b and e) being used as inputs can be interlinked with the operation of peripheral modules. table 1.1 outline of specifications (3/9) classification module/function description
rx64m group 1. overview under development preliminary document specifications in this document are tentative and subject to change. r01ds0173ej0090 rev.0.90 page 5 of 67 feb 28, 2014 timers 16-bit timer pulse unit (tpua) ? (16 bits 6 channels) 1 unit ? maximum of 16 pulse-input/output possible ? select from among seven or eight co unter-input clock signals for each channel ? input capture/output compare function ? output of pwm waveforms in up to 15 phases in pwm mode ? support for buffered operation, phase-counting mode (two phase encoder input) and cascade-connected operation (32 bits 2 channels) depending on the channel. ? ppg output trigger can be generated ? capable of generating conversion start triggers for the a/d converters ? digital filtering of signals from the input capture pins ? event linking by the elc timers multifunction timer pulse unit (mtu3a) ? 9 channels (16 bits 8 c hannels, 32 bits 1 channel) ? maximum of 16 pulse-input/out put and 3 pulse-input possible ? select from among 13 counter-input clock signals for each channel (pclka/1, pclka/ 2, pclka/4, pclka/8, pclka/16, pclk/a32, pclka/64, pclka/256, pclka/1024, mtclka, mtclkb, mtclkc, mtclkd) 11 of the signals are available for channels 1, 3 and 4, 12 are available for channel 2, and 9 are available for channels 5 to 8. ? input capture function ? 39 output compare/input capture registers ? counter clear operation (synchronous clear ing by compare match/input capture) ? simultaneous writing to multiple timer counters (tcnt) ? simultaneous register input/output by synchronous counter operation ? buffered operation ? support for cascade-connected operation ? 43 interrupt sources ? automatic transfer of register data ? pulse output mode toggle/pwm/complementary pw m/reset-synchronized pwm ? complementary pwm output mode outputs non-overlapping waveforms for controlling 3-phase inverters automatic specification of dead times pwm duty cycle: selectable as any value from 0% to 100% delay can be applied to requests for a/d conversion. non-generation of interrupt requests at peak or trough values of counters can be selected. double buffer configuration ? reset synchronous pwm mode three phases of positive and negative pwm waveforms can be output with desired duty cycles. ? phase-counting mode: 16-bit mode (channel s 1 and 2); 32-bit mode (channels 1 and 2) ? counter functionality for dead-time compensation ? generation of triggers for a/d converter conversion ? a/d converter start triggers can be skipped ? digital filter function for signals on the i nput capture and external counter clock pins ? ppg output trigger can be generated ? event linking by the elc port output enable 3 (poe3a) ? control of the high-impedance state of the mtu3/gpt's waveform output pins ? 5 pins for input from signal sources: poe0, poe4, poe8, poe10, poe11 ? initiation on detection of short-circuited outputs (detection of simultaneous pwm output to the active level) ? initiatio n by oscillation- stoppage detection or softw are ? additional programming of output control target pins is enabled table 1.1 outline of specifications (4/9) classification module/function description
rx64m group 1. overview under development preliminary document specifications in this document are tentative and subject to change. r01ds0173ej0090 rev.0.90 page 6 of 67 feb 28, 2014 timers general pwm timer (gpta) ? 16 bits 4 channels ? counting up or down (saw-wave), counting up and down (triangle-wave) selectable for all channels ? four clock sources independent ly selectable for all channels (pclka/1, pclka/4, pclka/8, pclka/16) ? 2 input/output pins per channel ? 2 output compare/input capture registers per channel ? for the 2 output compare/input capture r egisters of each channel, 4 registers are provided as buffer registers and are capable of operating as comparison registers when buffering is not in use. ? in output compare operation, buffer switching can be at peaks or troughs, enabling the generation of laterally asymmetrically pwm waveforms. ? registers for setting up frame intervals on each channel (with capability for generating interrupts on overflow or underflow) ? synchronizable operation of the several counters ? modes of synchronized operation (synchroni zed, or displaced by desired times for phase shifting) ? generation of dead times in pwm operation ? through combination of three counters, generation of automatic three-phase pwm waveforms incorporating dead times ? starting, clearing, and stopping counters in re sponse to external or internal triggers ? internal trigger sources: output of the internal comparator detection, software, and compare-match ? digital filter function for signals on the input capture and external trigger pins ? event linking by the elc programmable pulse generator (ppg) ? (4 bits 4 groups) 2 units ? pulse output with the mtu or tpu output as a trigger ? maximum of 32 pulse-output possible 8-bit timers (tmrb) ? (8 bits 2 channels) 2 units ? select from among seven internal cloc k signals (pclkb/1, pclkb/2, pclkb/8, pclkb/32, pclkb/64, pclkb/1024, pclkb/8192) and one external clock signal ? capable of output of pulse trains with desired duty cycles or of pwm signals ? the 2 channels of each unit can be cascaded to create a 16-bit timer ? generation of triggers for a/d converter conversion ? capable of generating baud-rate clocks for sci5, sci6, and sci12 ? event linking by the elc compare match timer (cmt) ? (16 bits 2 channels) 2 units ? select from among four internal cloc k signals (pclkb/8, pclkb/32, pclkb/128, pclkb/512) compare match timer w (cmtw) ? (32 bits 1 channel) 2 units ? compare-match, input-capture input, and output-comparison output are available. ? select from among four internal cloc k signals (pclkb/8, pclkb/32, pclkb/128, pclkb/512) ? interrupt requests can be output in response to compare-match, input-capture, and output-comparison events. ? event linking by the elc realtime clock ( rtcd) ? cloc k sources: main clock, sub clock ? selection of the 32-bit binary count in time count/second unit possible ? clock and calendar functions ? interrupt sources: alarm interrupt, periodic interrupt, and carry interrupt ? battery backup operation ? time-capture facility for three values ? event linking by the elc watchdog timer (wdta) ? 14 bits 1 channel ? select from among 6 counter-input clock signals (pclkb/4, pclkb/64, pclkb/128, pclkb/512, pclkb/2048, pclkb/8192) independent watchdog timer (iwdta) ? 14 bits 1 channel ? counter-input clock: iwdt-dedicated on-chip oscillator ? dedicated clock/1, dedicated clock/16, dedicated clock/32, dedicated clock/64, dedicated clock/128, dedicated clock/256 ? window function: the positions where the wi ndow starts and ends are specifiable (the window defines the timing with which refreshing is enabled and disabled). ? event linking by the elc table 1.1 outline of specifications (5/9) classification module/function description
rx64m group 1. overview under development preliminary document specifications in this document are tentative and subject to change. r01ds0173ej0090 rev.0.90 page 7 of 67 feb 28, 2014 communication function ethernet controller (etherc) ? 2 channels ? input and output of ethernet/ieee 802.3 frames ? transfer at 10 or 100 mbps ? full- and half-duplex modes ? mii (media independent interface) or rmii (reduced media independent interface) as defined in ieee 802.3u ? detection of magic packets tm * 1 or output of a "wake-on-lan" signal (wol) ? compliance with flow control as defined in ieee 802.3x standards ? filtering of multicast frames ? direct transfer of frames between two channels by cut-through ptp controller for ethernet controller (ptp) ? a block compatible with the ieee 1588 standard is connected to the ethernet controller (etherc). ? matching with a time stamp can st art counting by mtu3 and the gpt. dma controller for ethernet controller (edmac) ? 3 channels (the round-robin method determ ines the priority of the channels) 2 channels for etherc; 1 channel for eptpc ? alleviation of cpu load by the descriptor control method ? transmission fifo: 2 kbytes; reception fifo: 4 kbytes usb 2.0 fs host/ function module (usbb) ? includes a udc (usb device controller) and transceiver for usb 2.0 fs ? one port ? compliance with the usb 2.0 specification ? transfer rate: full speed (12 mbps) ? self-power mode and bus power are selectable ? otg (on the go) operation is possible ? incorporates 2 kbytes of ram as a transfer buffer ? external pull-up and pull-down resistors are not required usb 2.0 fs host/ function module with battery charging (usba) ? includes a udc (usb device controller) and transceiver for usb 2.0 fs ? one port (only in 176-pin devices) ? compliance with the usb 2.0 specification ? transfer rate: full speed (12 mbps), low speed (1.5 mbps) (host only) ? self-power mode and bus power are selectable ? otg (on the go) operation is possible ? incorporates 8.5 kbytes of ram as a transfer buffer ? external pull-up and pull-down resistors are not required serial communications interfaces (scig, scih) ? 9 channels (scig: 8 channels + scih: 1 channel) ? scig serial communications modes: asynchronou s, clock synchronous, and smart-card interface multi-processor function on-chip baud rate generator allows selection of the desired bit rate choice of lsb-first or msb-first transfer average transfer rate clock can be input from tmr timers for sci5, sci6, and sci12 start-bit detection: level or edge detection is selectable. simple i 2 c simple spi 9-bit transfer mode bit rate modulation double-speed mode event linking by the elc (only on chanel 5) ? scih (the following functions are added to scig) supports the serial communications protoc ol, which contains the start frame and information frame supports the lin format serial communications interface with fifo (scifa) ? 4 channels ? methods of transfer: asynchronous and clock synchronous ? desired bit rates can be selected from the internal baud rate generators. ? lsb or msb first is selectable. ? both the transmission and reception secti ons are equipped with 16-byte fifo buffers, allowing continuous transmission and reception. ? bit rate modulation ? double-speed mode table 1.1 outline of specifications (6/9) classification module/function description
rx64m group 1. overview under development preliminary document specifications in this document are tentative and subject to change. r01ds0173ej0090 rev.0.90 page 8 of 67 feb 28, 2014 communication function i 2 c bus interface (riica) ? 2 channels (only channel 0 can be used in fast-mode plus) communication formats i 2 c bus format/smbus format supports the multi-master max. transfer rate: 1 mbps (channel 0) ? event linking by the elc can module (can) ? 3 channels ? compliance with the iso11898-1 specific ation (standard frame and extended frame) ? 32 mailboxes per channel serial peripheral interface (rspia) ? 1 channel ? rspi transfer facility using the mosi (master out, slave in), miso (master in, slave out), ssl (slave select), and rspck (rspi clock) signals enables se rial transfer through spi operation (four lines) or clock-synchr onous operation (three lines) capable of handling serial transfer as a master or slave ? data formats switching between msb first and lsb first the number of bits in each transfer can be changed to any number of bits from 8 to 16, or to 20, 24, or 32 bits. 128-bit buffers for transmission and reception up to four frames can be transmitted or received in a single transfer operation (with each frame having up to 32 bits) ? buffered structure double buffers for both transmission and reception ? rspck can be stopped with the receive buffer full for master reception. ? event linking by the elc quad serial peripheral interface (qspi) ? 1 channel ? connectable with serial flash memory equipped with multiple input and output lines (i.e. for single, dual, or quad operation) ? programmable bit length and selectable acti ve sense and phase of the clock signal ? sequential execution of transfer ? lsb or msb first is selectable. serial sound interface (ssi) ? 2 channels ? full-duplex transfer is possible (only on channel 0). ? support for multiple audio formats ? support for master or slave operation ? bit clock frequency is selectable from four di fferent types (16 fs, 32 fs, 48 fs, and 64 fs). ? support for 8-/16-/18-/20-/22-/24 bit data formats ? internal 8-stage fifo for transmission and reception ? stopping ssiws when data transfer is stopped is selectable. sampling rate converter (src) ? 1 channel ? data formats: 32-bit stereo (16 bits for t he left, 16 bits for the right) and 16-bit monaural. ? input sampling rates: 8, 11.025, 12, 16, 22.05, 24, 32, 44.1, 48 khz ? output sampling rates: 32, 44.1, 48, 8* 2 or 16 khz* 2 sd host interface (sdhi)* 3 ? 1 channel ? one interface for sd memory and i/o cards (supporting 1- and 4-bit sd buses) ? sd specifications part 1: physical layer specification ver.3.01 compliant (ddr not supported) part e1: sdio specification ver. 3.00 ? error checking: crc7 for commands and crc16 for data ? interrupt requests: card access interrupt, sdio access interrupt, card detection interrupt ? dma transfer requests: sd_buf write and sd_buf read ? support for card detection and write protection mmc host interface (mmcif) ? 1 channel ? compliant with jedec standard je sd84-a441 (ddr is not supported) ? interface for multimedia cards (mmcs) ? device buses: support for 1-, 4-, and 8-bit mmc buses ? interrupt requests: card detection interrupt, error/timeout interrupt, normal operation interrupt ? dma transfer requests: ce_data write and ce_data read ? support for card detection, boot operation, high priority interrupt (hpi) table 1.1 outline of specifications (7/9) classification module/function description
rx64m group 1. overview under development preliminary document specifications in this document are tentative and subject to change. r01ds0173ej0090 rev.0.90 page 9 of 67 feb 28, 2014 parallel data capture unit (pdc) ? 1 channel ? acquisition of synchronization through external 8-bit horizontal and vertical synchronization signals ? setting of the image size when clipping of the output for a one-frame image is required 12-bit a/d converter (s12adc) ? 12 bits 2 units (unit 0: 8 channels; unit 1: 21 channels) ? 12-bit resolution (switchable between 8, 10, and 12 bits) ? conversion time (tbd) per channel (for 12-bit conversion) (tbd) per channel (for 10-bit conversion) (tbd) per channel (for 8-bit conversion) ? operating mode scan mode (single scan mode, continuous scan mode, or group scan mode) group a priority control (only for group scan mode) ? sample-and-hold function common sample-and-hold circuit included in addition, channel-dedicated sample-and-hold function (3ch: in unit 0 only) included ? sampling variable sampling time can be set up for each channel. ? digital comparison method: comparison to detect voltages above or below thresholds and window comparison measurement: comparison of two results of conversion or comparison of a value in the comparison register and a result of conversion ? self-diagnostic function the self-diagnostic function internally gener ates three analog input voltages (unit 0: vrefl0, vrefh0 1/2, vrefh0; unit 1: avss1, avcc1 1/2, avcc1) ? double trigger mode (a/d conversion data duplicated) ? detection of analog input disconnection ? three ways to start a/d conversion software trigger, timer (mtu3, gpt, tmr, tpu) trigger, external trigger ? event linking by the elc 12-bit d/a converter (r12da) ? 2 channels ? 12-bit resolution ? output voltage: 0.2 v to avcc1 ?? 0.2 v (amplifier output), 0 v to avcc1 (direct output) ? output via an amplifier or direct output can be selected. ? event linking by the elc temperature sensor ? 1 channel ? relative precision: 1c ? the voltage of the temperature is converted into a digital value by the 12-bit a/d converter (unit 1). safety memory protection unit (mpu) ? protection area: eight areas (max.) can be specified in the range from 0000 0000h to ffff ffffh. ? minimum protection unit: 16 bytes ? reading from, writing to, and enabling the ex ecution access can be specified for each area. ? an address exception occurs when the detected access is not in the permitted area. register write protection function ? protects important registers from being overwritten for in case a program runs out of control. crc calculator (crc) ? crc code generation for arbitrary amounts of data in 8-bit units ? select any of three generating polynomials: x 8 + x 2 + x + 1, x 16 + x 15 + x 2 + 1, or x 16 + x 12 + x 5 + 1 ? generation of crc codes for use with lsb- first or msb-first communications is selectable main clock oscillation stop function ? main clock oscillation stop detection: available clock frequency accuracy measurement circuit (cac) ? monitors the clock output from the main cloc k oscillator, sub-clo ck oscillator, low- and high-speed on-chip oscillators, the pll fr equency synthesizer, iw dt-dedicated on-chip oscillator, and pclkb, and generates interr upts when the setting range is exceeded. data operation circuit (doc) ? the function to compare, add, or subtract 16-bit data table 1.1 outline of specifications (8/9) classification module/function description
rx64m group 1. overview under development preliminary document specifications in this document are tentative and subject to change. r01ds0173ej0090 rev.0.90 page 10 of 67 feb 28, 2014 note 1. magic packet tm is a registered trademark of advanced micro devices, inc. note 2. setting is only possible when the input sampling rate 44.1 khz is selected. note 3. optional encryption function aes* 3 ? key lengths: 128, 196, and 256 bits ? support for cfb, ofb, and cmac operating modes ? speed of calculations: 128-bi t key length in 22 cycles 192-bit key length in 26 cycles 256-bit key length in 30 cycles ? compliant with fips pub 197 des* 3 ? key lengths: 56 bits (des)/3 56 bits (t-des) ? support for des and triple des ? support for ecb and cbc operating modes ? speed of calculations: 6 cloc k cycles in single des mode 14 clock cycles in triple des mode ? compliant with fips pub 46-3 ? compliant with fips pub 81 sha* 3 ? support for sha-1 (128), sha-2 (224 or 256), and hmac (160, 224, or 256) ? speed of calculations: 50 cl ock cycles in sha-1 mode 42 clock cycles in sha-224 mode 42 clock cycles in sha-256 mode ? compliant with sha as defined in fips pub 180-1 and -2 ? compliant with hmac as defined in fips pub 198 true random number generator (rng)* 3 ? length of random numbers: 16 bits ? generation of random-number-generated interrupts after a number is generated ? random number generation time: 2.8 ms (typ) operating frequency up to 120 mhz power supply voltage vcc = avcc0 = avcc1 = vcc_usb = 2.7 to 3.6 v, vrefh0 = 2.7 to avcc0, vcc_usba = avcc_usba = 2.7 to 3.6 v, v batt = 2.0 to 3.6 v operating temperature d-version: ? 40 to +85c g-version: ? 40 to +tbd package 177-pin tflga (ptlg0177ka-a) (in planning) 176-pin lfbga (plbg0176ga-a) (in planning) 176-pin lqfp (plqp0176kb-a) 145-pin tflga (ptlg0145ka-a) (in planning) 144-pin lqfp (plqp0144ka-a) 100-pin tflga (ptlg0100ja-a) (in planning) 100-pin lqfp (plqp0100kb-a) on-chip debugging system ? e1 emulator (jtag and fine interfaces) ? e20 emulator (jtag interface) table 1.1 outline of specifications (9/9) classification module/function description
rx64m group 1. overview under development preliminary document specifications in this document are tentative and subject to change. r01ds0173ej0090 rev.0.90 page 11 of 67 feb 28, 2014 table 1.2 comparison of functions for different packages (1/2) functions rx64m group package 177 pins, 176 pins 145 pins, 144 pins 100 pins external bus external bus width 32 bits 16 bits sdram area controller available not supported dma dma controller ch. 0 to 7 data transfer controller available exdma controller ch. 0 and 1 timers 16-bit timer pulse unit ch. 0 to 5 multi-function timer pulse unit 3 ch. 0 to 8 general-purpose pwm timer ch. 0 to 3 port output enable 3 available programmable pulse generator ch. 0 and 1 8-bit timers ch. 0 to 3 compare match timer ch. 0 to 3 compare match timer w ch. 0 and 1 realtime clock available watchdog timer available independent watchdog timer available communication function ethernet controller ch. 0 and 1 ch. 0 ptp controller for ethernet controller available dmac controller for ethernet ch. 0 and 1 (etherc) ch. 2 (eptpc) ch. 0 (etherc) and 2 (eptpc) usb 2.0 fs host/function module ch. 0 usb 2.0 fs host/function module with battery charging available not supported serial communications interfaces (scig) ch. 0 to 7 ch. 0 to 3, 5 and 6 serial communications interfaces (scih) ch. 12 serial communications interfaces with fifo ch. 8 to 11 ch. 8 and 9 i 2 c bus interfaces ch. 0 and 2 serial peripheral interface ch. 0 can module ch. 0 to 2 ch. 0 and 1 quad serial peripheral interface ch. 0 serial sound interfaces ch. 0 and 1 sampling rate converter available sd host interface ch. 0 mmc host interface ch. 0 parallel data capture unit available not supported 12-bit a/d converter an000 to 007 (unit 0: 8 channels) an100 to 120 (unit 1: 21 channels) an000 to 007 (unit 0: 8 channels) an100 to 113 (unit 1: 14 channels) 12-bit d/a converter ch. 0 and 1 ch. 1 temperature sensor available crc calculator available data operation circuit available clock frequency accuracy m easurement circuit available aes available
rx64m group 1. overview under development preliminary document specifications in this document are tentative and subject to change. r01ds0173ej0090 rev.0.90 page 12 of 67 feb 28, 2014 des available sha available rng available event link controller available table 1.2 comparison of functions for different packages (2/2) functions rx64m group package 177 pins, 176 pins 145 pins, 144 pins 100 pins
rx64m group 1. overview under development preliminary document specifications in this document are tentative and subject to change. r01ds0173ej0090 rev.0.90 page 13 of 67 feb 28, 2014 1.2 list of products table 1.3 is a list of products, and figure 1.1 shows how to read the product part no. table 1.3 list of products (1/3) group part no. package code flash memory capacity ram capacity data flash memory capacity operating frequency (max.) encryption module sdhi rx64m r5f564mlcdfc plqp0176kb-a 4 mbytes 512 kbytes 64 kbytes 120 mhz not supported not supported r5f564mlddfc plqp0176kb-a 4 mbytes 512 kbytes 64 kbytes 120 mhz not supported available r5f564mlgdfc plqp0176kb-a 4 mbytes 512 kbytes 64 kbytes 120 mhz available not supported r5f564mlhdfc plqp0176kb-a 4 mbytes 512 kbytes 64 kbytes 120 mhz available available r5f564mjcdfc plqp0176kb-a 3 mbytes 512 kbytes 64 kbytes 120 mhz not supported not supported r5f564mjddfc plqp0176kb-a 3 mbytes 512 kbytes 64 kbytes 120 mhz not supported available r5f564mjgdfc plqp0176kb-a 3 mbytes 512 kbytes 64 kbytes 120 mhz available not supported r5f564mjhdfc plqp0176kb-a 3 mbytes 512 kbytes 64 kbytes 120 mhz available available r5f564mgcdfc plqp0176kb-a 2.5 mbytes 512 kbytes 64 kbytes 120 mhz not supported not supported r5f564mgddfc plqp0176kb-a 2.5 mbytes 512 kbytes 64 kbytes 120 mhz not supported available r5f564mggdfc plqp0176kb-a 2.5 mbytes 512 kbytes 64 kbytes 120 mhz available not supported r5f564mghdfc plqp0176kb-a 2.5 mbytes 512 kbytes 64 kbytes 120 mhz available available r5f564mfcdfc plqp0176kb-a 2 mbytes 512 kbytes 64 kbytes 120 mhz not supported not supported r5f564mfddfc plqp0176kb-a 2 mbytes 512 kbytes 64 kbytes 120 mhz not supported available r5f564mfgdfc plqp0176kb-a 2 mbytes 512 kbytes 64 kbytes 120 mhz available not supported r5f564mfhdfc plqp0176kb-a 2 mbytes 512 kbytes 64 kbytes 120 mhz available available r5f564mlcdfb plqp0144ka-a 4 mbytes 512 kbytes 64 kbytes 120 mhz not supported not supported r5f564mlddfb plqp0144ka-a 4 mbytes 512 kbytes 64 kbytes 120 mhz not supported available r5f564mlgdfb plqp0144ka-a 4 mbytes 512 kbytes 64 kbytes 120 mhz available not supported r5f564mlhdfb plqp0144ka-a 4 mbytes 512 kbytes 64 kbytes 120 mhz available available r5f564mjcdfb plqp0144ka-a 3 mbytes 512 kbytes 64 kbytes 120 mhz not supported not supported r5f564mjddfb plqp0144ka-a 3 mbytes 512 kbytes 64 kbytes 120 mhz not supported available r5f564mjgdfb plqp0144ka-a 3 mbytes 512 kbytes 64 kbytes 120 mhz available not supported r5f564mjhdfb plqp0144ka-a 3 mbytes 512 kbytes 64 kbytes 120 mhz available available r5f564mgcdfb plqp0144ka-a 2.5 mbytes 512 kbytes 64 kbytes 120 mhz not supported not supported r5f564mgddfb plqp0144ka-a 2.5 mbytes 512 kbytes 64 kbytes 120 mhz not supported available r5f564mggdfb plqp0144ka-a 2.5 mbytes 512 kbytes 64 kbytes 120 mhz available not supported r5f564mghdfb plqp0144ka-a 2.5 mbytes 512 kbytes 64 kbytes 120 mhz available available r5f564mfcdfb plqp0144ka-a 2 mbytes 512 kbytes 64 kbytes 120 mhz not supported not supported r5f564mfddfb plqp0144ka-a 2 mbytes 512 kbytes 64 kbytes 120 mhz not supported available r5f564mfgdfb plqp0144ka-a 2 mbytes 512 kbytes 64 kbytes 120 mhz available not supported r5f564mfhdfb plqp0144ka-a 2 mbytes 512 kbytes 64 kbytes 120 mhz available available r5f564mlcdfp plqp0100kb-a 4 mbytes 512 kbytes 64 kbytes 120 mhz not supported not supported r5f564mlddfp plqp0100kb-a 4 mbytes 512 kbytes 64 kbytes 120 mhz not supported available r5f564mlgdfp plqp0100kb-a 4 mbytes 512 kbytes 64 kbytes 120 mhz available not supported r5f564mlhdfp plqp0100kb-a 4 mbytes 512 kbytes 64 kbytes 120 mhz available available r5f564mjcdfp plqp0100kb-a 3 mbytes 512 kbytes 64 kbytes 120 mhz not supported not supported r5f564mjddfp plqp0100kb-a 3 mbytes 512 kbytes 64 kbytes 120 mhz not supported available r5f564mjgdfp plqp0100kb-a 3 mbytes 512 kbytes 64 kbytes 120 mhz available not supported r5f564mjhdfp plqp0100kb-a 3 mbytes 512 kbytes 64 kbytes 120 mhz available available r5f564mgcdfp plqp0100kb-a 2.5 mbytes 512 kbytes 64 kbytes 120 mhz not supported not supported r5f564mgddfp plqp0100kb-a 2.5 mbytes 512 kbytes 64 kbytes 120 mhz not supported available r5f564mggdfp plqp0100kb-a 2.5 mbytes 512 kbytes 64 kbytes 120 mhz available not supported r5f564mghdfp plqp0100kb-a 2.5 mbytes 512 kbytes 64 kbytes 120 mhz available available
rx64m group 1. overview under development preliminary document specifications in this document are tentative and subject to change. r01ds0173ej0090 rev.0.90 page 14 of 67 feb 28, 2014 rx64m r5f564mfcdfp plqp0100kb-a 2 mbytes 512 kbytes 64 kbytes 120 mhz not supported not supported r5f564mfddfp plqp0100kb-a 2 mbytes 512 kbytes 64 kbytes 120 mhz not supported available r5f564mfgdfp plqp0100kb-a 2 mbytes 512 kbytes 64 kbytes 120 mhz available not supported r5f564mfhdfp plqp0100kb-a 2 mbytes 512 kbytes 64 kbytes 120 mhz available available r5f564mlcdbg plbg0176ga-a 4 mbytes 512 kbytes 64 kbytes 120 mhz not supported not supported r5f564mlddbg plbg0176ga-a 4 mbytes 512 kbytes 64 kbytes 120 mhz not supported available r5f564mlgdbg plbg0176ga-a 4 mbytes 512 kbytes 64 kbytes 120 mhz available not supported R5F564MLHDBG plbg0176ga-a 4 mbytes 512 kbytes 64 kbytes 120 mhz available available r5f564mjcdbg plbg0176ga-a 3 mbytes 512 kbytes 64 kbytes 120 mhz not supported not supported r5f564mjddbg plbg0176ga-a 3 mbytes 512 kbytes 64 kbytes 120 mhz not supported available r5f564mjgdbg plbg0176ga-a 3 mbytes 512 kbytes 64 kbytes 120 mhz available not supported r5f564mjhdbg plbg0176ga-a 3 mbytes 512 kbytes 64 kbytes 120 mhz available available r5f564mgcdbg plbg0176ga-a 2.5 mbytes 512 kbytes 64 kbytes 120 mhz not supported not supported r5f564mgddbg plbg0176ga-a 2.5 mbytes 512 kbytes 64 kbytes 120 mhz not supported available r5f564mggdbg plbg0176ga-a 2.5 mbytes 512 kbytes 64 kbytes 120 mhz available not supported r5f564mghdbg plbg0176ga-a 2.5 mbytes 512 kbytes 64 kbytes 120 mhz available available r5f564mfcdbg plbg0176ga-a 2 mbytes 512 kbytes 64 kbytes 120 mhz not supported not supported r5f564mfddbg plbg0176ga-a 2 mbytes 512 kbytes 64 kbytes 120 mhz not supported available r5f564mfgdbg plbg0176ga-a 2 mbytes 512 kbytes 64 kbytes 120 mhz available not supported r5f564mfhdbg plbg0176ga-a 2 mbytes 512 kbytes 64 kbytes 120 mhz available available r5f564mlcdlc ptlg0177ka-a* 1 4 mbytes 512 kbytes 64 kbytes 120 mhz not supported not supported r5f564mlddlc ptlg0177ka-a* 1 4 mbytes 512 kbytes 64 kbytes 120 mhz not supported available r5f564mlgdlc ptlg0177ka-a* 1 4 mbytes 512 kbytes 64 kbytes 120 mhz available not supported r5f564mlhdlc ptlg0177ka-a* 1 4 mbytes 512 kbytes 64 kbytes 120 mhz available available r5f564mjcdlc ptlg0177ka-a* 1 3 mbytes 512 kbytes 64 kbytes 120 mhz not supported not supported r5f564mjddlc ptlg0177ka-a* 1 3 mbytes 512 kbytes 64 kbytes 120 mhz not supported available r5f564mjgdlc ptlg0177ka-a* 1 3 mbytes 512 kbytes 64 kbytes 120 mhz available not supported r5f564mjhdlc ptlg0177ka-a* 1 3 mbytes 512 kbytes 64 kbytes 120 mhz available available r5f564mgcdlc ptlg0177ka-a* 1 2.5 mbytes 512 kbytes 64 kbytes 120 mhz not supported not supported r5f564mgddlc ptlg0177ka-a* 1 2.5 mbytes 512 kbytes 64 kbytes 120 mhz not supported available r5f564mggdlc ptlg0177ka-a* 1 2.5 mbytes 512 kbytes 64 kbytes 120 mhz available not supported r5f564mghdlc ptlg0177ka-a* 1 2.5 mbytes 512 kbytes 64 kbytes 120 mhz available available r5f564mfcdlc ptlg0177ka-a* 1 2 mbytes 512 kbytes 64 kbytes 120 mhz not supported not supported r5f564mfddlc ptlg0177ka-a* 1 2 mbytes 512 kbytes 64 kbytes 120 mhz not supported available r5f564mfgdlc ptlg0177ka-a* 1 2 mbytes 512 kbytes 64 kbytes 120 mhz available not supported r5f564mfhdlc ptlg0177ka-a* 1 2 mbytes 512 kbytes 64 kbytes 120 mhz available available r5f564mlcdlk ptlg0145ka-a* 1 4 mbytes 512 kbytes 64 kbytes 120 mhz not supported not supported r5f564mlddlk ptlg0145ka-a* 1 4 mbytes 512 kbytes 64 kbytes 120 mhz not supported available r5f564mlgdlk ptlg0145ka-a* 1 4 mbytes 512 kbytes 64 kbytes 120 mhz available not supported r5f564mlhdlk ptlg0145ka-a* 1 4 mbytes 512 kbytes 64 kbytes 120 mhz available available r5f564mjcdlk ptlg0145ka-a* 1 3 mbytes 512 kbytes 64 kbytes 120 mhz not supported not supported r5f564mjddlk ptlg0145ka-a* 1 3 mbytes 512 kbytes 64 kbytes 120 mhz not supported available r5f564mjgdlk ptlg0145ka-a* 1 3 mbytes 512 kbytes 64 kbytes 120 mhz available not supported r5f564mjhdlk ptlg0145ka-a* 1 3 mbytes 512 kbytes 64 kbytes 120 mhz available available r5f564mgcdlk ptlg0145ka-a* 1 2.5 mbytes 512 kbytes 64 kbytes 120 mhz not supported not supported r5f564mgddlk ptlg0145ka-a* 1 2.5 mbytes 512 kbytes 64 kbytes 120 mhz not supported available r5f564mggdlk ptlg0145ka-a* 1 2.5 mbytes 512 kbytes 64 kbytes 120 mhz available not supported r5f564mghdlk ptlg0145ka-a* 1 2.5 mbytes 512 kbytes 64 kbytes 120 mhz available available table 1.3 list of products (2/3) group part no. package code flash memory capacity ram capacity data flash memory capacity operating frequency (max.) encryption module sdhi
rx64m group 1. overview under development preliminary document specifications in this document are tentative and subject to change. r01ds0173ej0090 rev.0.90 page 15 of 67 feb 28, 2014 note 1. under planning rx64m r5f564mfcdlk ptlg0145ka-a* 1 2 mbytes 512 kbytes 64 kbytes 120 mhz not supported not supported r5f564mfddlk ptlg0145ka-a* 1 2 mbytes 512 kbytes 64 kbytes 120 mhz not supported available r5f564mfgdlk ptlg0145ka-a* 1 2 mbytes 512 kbytes 64 kbytes 120 mhz available not supported r5f564mfhdlk ptlg0145ka-a* 1 2 mbytes 512 kbytes 64 kbytes 120 mhz available available r5f564mlcdlj ptlg0100ja-a* 1 4 mbytes 512 kbytes 64 kbytes 120 mhz not supported not supported r5f564mlddlj ptlg0100ja-a* 1 4 mbytes 512 kbytes 64 kbytes 120 mhz not supported available r5f564mlgdlj ptlg0100ja-a* 1 4 mbytes 512 kbytes 64 kbytes 120 mhz available not supported r5f564mlhdlj ptlg0100ja-a* 1 4 mbytes 512 kbytes 64 kbytes 120 mhz available available r5f564mjcdlj ptlg0100ja-a* 1 3 mbytes 512 kbytes 64 kbytes 120 mhz not supported not supported r5f564mjddlj ptlg0100ja-a* 1 3 mbytes 512 kbytes 64 kbytes 120 mhz not supported available r5f564mjgdlj ptlg0100ja-a* 1 3 mbytes 512 kbytes 64 kbytes 120 mhz available not supported r5f564mjhdlj ptlg0100ja-a* 1 3 mbytes 512 kbytes 64 kbytes 120 mhz available available r5f564mgcdlj ptlg0100ja-a* 1 2.5 mbytes 512 kbytes 64 kbytes 120 mhz not supported not supported r5f564mgddlj ptlg0100ja-a* 1 2.5 mbytes 512 kbytes 64 kbytes 120 mhz not supported available r5f564mggdlj ptlg0100ja-a* 1 2.5 mbytes 512 kbytes 64 kbytes 120 mhz available not supported r5f564mghdlj ptlg0100ja-a* 1 2.5 mbytes 512 kbytes 64 kbytes 120 mhz available available r5f564mfcdlj ptlg0100ja-a* 1 2 mbytes 512 kbytes 64 kbytes 120 mhz not supported not supported r5f564mfddlj ptlg0100ja-a* 1 2 mbytes 512 kbytes 64 kbytes 120 mhz not supported available r5f564mfgdlj ptlg0100ja-a* 1 2 mbytes 512 kbytes 64 kbytes 120 mhz available not supported r5f564mfhdlj ptlg0100ja-a* 1 2 mbytes 512 kbytes 64 kbytes 120 mhz available available table 1.3 list of products (3/3) group part no. package code flash memory capacity ram capacity data flash memory capacity operating frequency (max.) encryption module sdhi
rx64m group 1. overview under development preliminary document specifications in this document are tentative and subject to change. r01ds0173ej0090 rev.0.90 page 16 of 67 feb 28, 2014 figure 1.1 how to read the product part number r5f564mlcdfc package type, number of pins, and pin pitch fc: lqfp/176/0.50 bg: lfbga/176/0.80 lc: tflga/177/0.50 fb: lqfp/144/0.50 lk: tflga/145/0.50 fp: lqfp/100/0.50 lj: tflga/100/0.65 d: operating peripheral temperature: ?40 to +85c g: operating peripheral temperature: ?40 to tbd d: encryption module not included, sdhi module included h: encryption module included, sdhi module included c: encryption module not included, sdhi module not included g: encryption module included, sdhi module not included code flash memory, ram, and data flash memory capacity l: 4 mbytes/512 kbytes/64 kbytes j: 3 mbyte/512 kbytes/64 kbytes g: 2.5 mbytes/512 kbytes/64 kbytes f: 2 mbytes/512 kbytes/64 kbytes group name 4m: rx64m group series name rx600 series type of memory f: flash memory version renesas mcu renesas semiconductor product
rx64m group 1. overview under development preliminary document specifications in this document are tentative and subject to change. r01ds0173ej0090 rev.0.90 page 17 of 67 feb 28, 2014 1.3 block diagram figure 1.2 shows a block diagram. figure 1.2 block diagram aes *1 scifa 4 channels usba rspia mtu3a 8 channels gpta 4 channels eptpc etherc 2 channels external bus bsc clock generation circuit rx cpu code flash memory ram port 0 port 1 port 2 port 3 port 4 port 5 port 6 port 7 port 8 port 9 port a port b port c dtca dmacaa 8 channels icua port d port e port f port g port j mpu edmaca 3 channels ram with ecc operand bus instruction bus internal main bus 1 internal main bus 2 exdmaca temperature sensor 12-bit dac 2 channels riica 2 channels rtcd cmtw 1 channel (unit 1) cmtw 1 channel (unit 0) cmt 2 channels (unit 1) cmt 2 channels (unit 0) tmrb 2 channels (unit 1) tmrb 2 channels (unit 0) ppg (unit 1) ppg (unit 0) tpua 6 channels (unit 0) poe3a can 3 channels usbb 1 port scih 1 channel scig 8 channels crc doc cac iwdta wdta pdc mmcif sdhi *1 qspi rng *1 data flash memory standby ram des *1 sha *1 12-bit adc 21 channels (unit 1) 12-bit adc 8 channels (unit 0) internal peripheral buses 1 to 6 src ssi 2ch etherc: ethernet controller eptpc: ptp controller for ethernet controller edmac: dma controller for ethernet controller icua: interrupt controller dtca: data transfer controller dmacaa: dma controller exdmaca: exdma controller bsc: bus controller wdta: watchdog timer iwdta: independent watchdog timer crc: crc (cyclic redundancy check) calculator sci: serial communications interface scifa: serial communications interface with fifo usbb: usb2.0 fs host/function module usba: usb2.0 fs host/function module with battery charging rspia: serial peripheral interface mpu: memory protection unit qspi: quad serial peripheral interface sdhi: sd host interface *1 mmcif: mmc host interface pdc: parallel data capture unit can: can module mtu3a: multi-function timer pulse unit 3 poe3a: port output enable 3 gpta: general-purpose pwm timer tpua: 16-bit timer pulse unit ppg: programmable pulse generator tmrb: 8-bit timer cmt: compare match timer cmtw: compare match timer w rtcd: realtime clock riica: i 2 c bus interface doc: data operation circuit cac: clock frequency accuracy measurement circuit aes: aes* 1 des: des* 1 sha: sha-256* 1 rng: true random number generator *1 ssi: serial sound interface src: sampling rate converter note 1. optional
rx64m group 1. overview under development preliminary document specifications in this document are tentative and subject to change. r01ds0173ej0090 rev.0.90 page 18 of 67 feb 28, 2014 1.4 pin functions table 1.4 lists the pin functions. table 1.4 pin functions (1/8) classifications pin name i/o description digital power supply vcc input power supply pin. c onnect this pin to the system power supply. connect the pin to vss via a 0.1- f multilayer ceramic capacitor. the capacitor shoul d be placed close to the pin. vcl input connect this pin to vss via a 0.1- f multilayer ceramic capacitor. the capacitor shoul d be placed close to the pin. vss input ground pin. connect it to the system power supply (0 v). vbatt input backup power pin clock xtal output pins for a crystal resonator. an external clock signal can be input through the extal pin. extal input bclk output outputs the external bus clock for external devices. sdclk output outputs the sdram-dedicated clock. xcout output input/output pins for the s ub clock oscillator. connect a crystal resonator between xcout and xcin. xcin input clock frequency accuracy measurement cacref input reference clock input pi n for the clock frequency accuracy measurement circuit operating mode control md input pins for setting t he operating mode. the signal levels on these pins must not be changed during operation. ub input usb boot mode or user boot mode enable pin upsel input selects the power supply method in usb boot mode. the low level selects self-power mode and the high level selects bus power mode. system control res# input reset signal input pin. this lsi enters the reset state when this signal goes low. emle input input pin for the on-chip emulator enable signal. when the on- chip emulator is used, this pin should be driven high. when not used, it should be driven low. bscanp input boundary scan enable pin. bo undary scan is enabled when this pin goes high. when not used, it should be driven low. on-chip emulator finec input fine interface clock pin fined i/o fine interface pin trst# input on-chip emulator or boundary scan pins. when the emle pin is driven high, these pins are dedicated for the on-chip emulator. tms input tdi input tck input tdo output trclk output this pin outputs the clock for synchronization with the trace data. trsync output this pin indicates that output from the trdata0 to trdata3 pins is valid. trdata0 to trdata3 output these pins output the trace information. address bus a0 to a23 output output pins for the address data bus d0 to d31 i/o input and output pins for the bidirectional data bus multiplexed bus a0/d0 to a15/d15 i/o address/data multiplexed bus
rx64m group 1. overview under development preliminary document specifications in this document are tentative and subject to change. r01ds0173ej0090 rev.0.90 page 19 of 67 feb 28, 2014 bus control rd# output strobe signal which indicates that reading from the external bus interface space is in progress wr# output strobe signal which indicates that writing to the external bus interface space is in prog ress, in 1-write strobe mode wr0# to wr3# output strobe signals which indicate that either group of data bus pins (d7 to d0, d15 to d8, d23 to d16 and d31 to d24) is valid in writing to the external bus interface space, in byte strobe mode bc0# to bc3# output strobe signals which indicate that either group of data bus pins (d7 to d0, d15 to d8, d23 to d16 and d31 to d24) is valid in access to the external bus interface space, in 1-write strobe mode ale output address latch signal when address/data multiplexed bus is selected wait# input input pin for wait request signal s in access to the external space cs0# to cs7# output select signals for cs areas exdma controller edreq0, edreq1 input external dma transfer request pins edack0, edack1 output single addr ess transfer acknowledge signals interrupt nmi input non-maskable interrupt request pin irq0 to irq15 input maskable interrupt request pins multi-function timer pulse unit 3 mtioc0a, mtioc0b mtioc0c, mtioc0d i/o the tgra0 to tgrd0 input capture input/output compare output/pwm output pins mtioc1a, mtioc1b i/o the tgra1 and tgrb1 input capture input/output compare output/pwm output pins mtioc2a, mtioc2b i/o the tgra2 and tgrb2 input capture input/output compare output/pwm output pins mtioc3a, mtioc3b mtioc3c, mtioc3d i/o the tgra3 to tgrd3 input capture input/output compare output/pwm output pins mtioc4a, mtioc4b mtioc4c, mtioc4d i/o the tgra4 to tgrd4 input capture input/output compare output/pwm output pins mtic5u, mtic5v mtic5w input the tgru5, tgrv5, and tgrw5 input capture input/dead time compensation input pins mtioc6a, mtioc6b mtioc6c, mtioc6d i/o the tgra6 to tgrd6 input capture input/output compare output/pwm output pins mtioc7a, mtioc7b mtioc7c, mtioc7d i/o the tgra7 to tgrd7 input capture input/output compare output/pwm output pins mtioc8a, mtioc8b mtioc8c, mtioc8d i/o the tgra8 to tgrd8 input capture input/output compare output/pwm output pins mtclka, mtclkb mtclkc, mtclkd input input pins for external clock signals or for phase counting mode clock signals port output enable 3 poe0#, poe4#, poe8#, poe10#, poe11# input input pins for request signals to place the mtu or gpt in the high impedance state table 1.4 pin functions (2/8) classifications pin name i/o description
rx64m group 1. overview under development preliminary document specifications in this document are tentative and subject to change. r01ds0173ej0090 rev.0.90 page 20 of 67 feb 28, 2014 general-purpose pwm timer gtioc0a-a/gtioc0a-b/ gtioc0a-c/gtioc0a-d/ gtioc0a-e, gtioc0b-a/gtioc0b-b/ gtioc0b-c/gtioc0b-d/ gtioc0b-e i/o gpt0.gtgra and gpt0.gtgrb input capture input/output compare output/pwm output pins gtioc1a-a/gtioc1a-b/ gtioc1a-c/gtioc1a-d/ gtioc1a-e, gtioc1b-a/gtioc1b-b/ gtioc1b-c/gtioc1b-d/ gtioc1b-e i/o gpt1.gtgra and gpt1.gtgrb input capture input/output compare output/pwm output pins gtioc2a-a/gtioc2a-b/ gtioc2a-c/gtioc2a-d/ gtioc2a-e, gtioc2b-a/gtioc2b-b/ gtioc2b-c/gtioc2b-d/ gtioc2b-e i/o gpt2.gtgra and gpt2.gtgrb input capture input/output compare output/pwm output pins gtioc3a-d/gtioc3a-e, gtioc3b-d/gtioc3b-e i/o gpt3.gtgra and gpt3.gtgrb input capture input/output compare output/pwm output pins gtetrg-b/gtetrg-c/ gtetrg-d input external trigger input pin for gpt0 to gpt3 16-bit timer pulse unit tioca0, tiocb0 tiocc0, tiocd0 i/o the tgra0 to tgrd0 input capture input/output compare output/pwm output pins tioca1, tiocb1 i/o the tgra1 and tgrb1 input capture input/output compare output/pwm output pins tioca2, tiocb2 i/o the tgra2 and tgrb2 input capture input/output compare output/pwm output pins tioca3, tiocb3 tiocc3, tiocd3 i/o the tgra3 to tgrd3 input capture input/output compare output/pwm output pins tioca4, tiocb4 i/o the tgra4 and tgrb4 input capture input/output compare output/pwm output pins tioca5, tiocb5 i/o the tgra5 and tgrb5 input capture input/output compare output/pwm output pins tclka, tclkb tclkc, tclkd input input pins for external clock signals or for phase counting mode clock signals programmable pulse generator po0 to po31 output output pins for the pulse signals 8-bit timer tmo0 to tmo3 output compare match output pins tmci0 to tmci3 input input pins for exter nal clocks to be input to the counter tmri0 to tmri3 input input pins for the counter reset compare match timer w tic0, tic1 input input pins for cmtw toc0, toc1 output output pins for cmtw table 1.4 pin functions (3/8) classifications pin name i/o description
rx64m group 1. overview under development preliminary document specifications in this document are tentative and subject to change. r01ds0173ej0090 rev.0.90 page 21 of 67 feb 28, 2014 serial communications interface (scig) ? asynchronous mode/cl ock synchronous mode sck0 to sck7 i/o input/output pins for the clock rxd0 to rxd7 input input pins for received data txd0 to txd7 output output pins for transmitted data cts0# to cts7# input input pins for control ling the start of transmission and reception rts0# to rts7# output output pins for c ontrolling the start of transmission and reception ? simple i 2 c mode sscl0 to sscl7 i/o input/output pins for the i 2 c clock ssda0 to ssda7 i/o input/output pins for the i 2 c data ? simple spi mode sck0 to sck7 i/o input/output pins for the clock smiso0 to smiso7 i/o input/output pins for slave transmission of data smosi0 to smosi7 i/o input/output pins for master transmission of data ss0# to ss7# input chip-select input pins serial communications interface (scih) ? asynchronous mode/cl ock synchronous mode sck12 i/o input/output pin for the clock rxd12 input input pin for received data txd12 output output pin for transmitted data cts12# input input pin for controlling the start of transmission and reception rts12# output output pin for controlling the start of transmission and reception ? simple i 2 c mode sscl12 i/o input/output pin for the i 2 c clock ssda12 i/o input/output pin for the i 2 c data ? simple spi mode sck12 i/o input/output pin for the clock smiso12 i/o input/output pin for slave transmission of data smosi12 i/o input/output pin for master transmission of data ss12# input chip-select input pin ? extended serial mode rxdx12 input input pin for received data txdx12 output output pin for transmitted data siox12 i/o input/output pin for received or transmitted data serial communications interface with fifo (scifa) sck8 to sck11 i/o input/output pins for the clock rxd8 to rxd11 input input pins for received data txd8 to txd11 output output pins for transmitted data cts8# to cts11# input input pins for control ling the start of transmission and reception rts8# to rts11# output output pins for controlling the start of transmission and reception i 2 c bus interface scl0[fm+], scl2 i/o input/output pins for clocks. bus can be dire ctly driven by the n- channel open drain sda0[fm+], sda2 i/o input/output pins for data. bus can be directly driven by the n- channel open drain table 1.4 pin functions (4/8) classifications pin name i/o description
rx64m group 1. overview under development preliminary document specifications in this document are tentative and subject to change. r01ds0173ej0090 rev.0.90 page 22 of 67 feb 28, 2014 ethernet controller ref50ck0, ref50ck1 input 50-mhz refe rence clocks. these pins input reference signals for transmission/reception timings in rmii mode. rmii0_crs_dv, rmii1_crs_dv input indicate that there are carrier detection signals and valid receive data on rmii_rxd1 and rmii_rxd0 in rmii mode. rmii0_txd0, rmii0_txd1, rmii1_txd0, rmii1_txd1 output 2-bit transmit data in rmii mode rmii0_rxd0, rmii0_rxd1, rmii1_rxd0, rmii1_rxd1 input 2-bit receive data in rmii mode rmii0_txd_en, rmii1_txd_en output output pins for data tr ansmit enable signals in rmii mode rmii0_rx_er, rmii1_rx_er input indicate an error has occurred during reception of data in rmii mode. et0_crs, et1_crs input carrier detection/data reception enable pins et0_rx_dv, et1_rx_dv input indicate that there are valid receive data on et_erxd3 to et_erxd0. et0_exout, et1_exout output general-purpose external output pins et0_linksta et1_linksta input input link status from the phy-lsi. et0_etxd0 to et0_etxd3, et1_etxd0 to et1_etxd3 output 4 bits of mii transmit data et0_erxd0 to et0_erxd3, et1_erxd0 to et1_erxd3 input 4 bits of mii receive data et0_tx_en, et1_tx_en output transmit enable pins. functi on as signals indicating that transmit data is ready on et_etxd3 to et_etxd0. et0_tx_er, et1_tx_er output transmit error pins. function as signals notifying the phy_lsi of an error during transmission. et0_rx_er, et1_rx_er input receive error pins. function as signals to recognize an error during reception. et0_tx_clk, et1_tx_clk input transmit clock pins. these pi ns input reference signals for output timings from et_tx_en, et_etxd3 to et_etxd0, and et_tx_er. et0_rx_clk, et1_rx_clk input receive clock pins. these pins input reference signals for input timings to et_rx_dv, et_erxd3 to et_erxd0, and et_rx_er. et0_col, et1_col input input collision detection signals. et0_wol, et1_wol output receive magic packets. et0_mdc, et1_mdc output output reference clock signals for information transfer via et_mdio. et0_mdio, et1_mdio i/o input or output bidirectional signals for exchange of management information between the rx64m group and the phy-lsi. table 1.4 pin functions (5/8) classifications pin name i/o description
rx64m group 1. overview under development preliminary document specifications in this document are tentative and subject to change. r01ds0173ej0090 rev.0.90 page 23 of 67 feb 28, 2014 usb 2.0 host/function module vcc_usb, vcc_usba input power supply pins vss_usb, vss1_usba, vss2_usba input ground pins avcc_usba input usba analog power supply pin avss_usba input usba analog ground pin. short this pin with the pvss_usba pin. pvss_usba input usba pll circuit ground pin. short this pin with the avss_usba pin. usba_rref i/o usba reference current supply pin. connect 2.2 k ? (1%) to the avss_usba pin. usb0_dp, usba_dp i/o input or output usb transceiver d+ data. usb0_dm, usba_dm i/o input or output usb transceiver d- data. usb0_exicen, usba_exicen output connect to the otg power ic. usb0_id, usba_id input connect to the otg power ic. usb0_vbusen usba_vbusen output usb vbus power enable pins usb0_ovrcura/ usb0_ovrcurb, usba_ovrcura/ usba_ovrcurb input usb overcurrent pins usb0_vbus, usba_vbus input usb cable connection/disc onnection detection input pins can module crx0, crx1-ds, crx2 input input pins ctx0 to ctx2 output output pins serial peripheral interface rspcka-a/rspcka-b i/o clock input/output pin mosia-a/mosia-b i/o inputs or outputs data output from the master misoa-a/misoa-b i/o inputs or outputs data output from the slave ssla0-a/ssla0-b i/o input or output pin for slave selection ssla1-a/ssla1-b to ssla3- a/ssla3-b output output pin for slave selection quad serial peripheral interface qspclk-a/-b output qspi clock output pin qssl-a/-b output qspi slave output pin qmo-a/-b, qio0-a/-b i/o master transmit data/data 0 qmi-a/-b, qio1-a/-b i/o master input data/data 1 qio2-a/-b, qio3-a/-b i/o data 2, data 3 serial sound interface ssisck0, ssi sck1 i/o ssi serial bit clock pins ssiws0, ssiws1 i/o word select pins ssitxd0, ssitxd1 output serial data output pins ssirxd0, ssirxd1 input serial data input pins ssidata0, ssidata1 i/o serial data input/output pins audio_mclk input master clock pin for audio table 1.4 pin functions (6/8) classifications pin name i/o description
rx64m group 1. overview under development preliminary document specifications in this document are tentative and subject to change. r01ds0173ej0090 rev.0.90 page 24 of 67 feb 28, 2014 mmc host interface mmc_clk-a/ mmc_clk-b output mmc clock pin mmc_cmd-a/ mmc_cmd-b i/o command/response pin mmc_d7-a/mmc_d7-b to mmc_d0-a/mmc_d0-b i/o transmit data/receive data mmc_cd-a/mmc_cd-b input card detection pin mmc_res#-a/mmc_res#-b output mmc reset output pin sd host interface sdhi_clk-a/sdhi_clk-b output sd clock output pin sdhi_cmd-a/sdhi_cmd-b i/o sd command output, response input signal pin sdhi_d3-a/sdhi_d3-b to sdhi_d0-a/sdhi_d0-b i/o sd data bus pins sdhi_cd-a/sdhi_cd-b input sd card detection pin sdhi_wp-a/sdhi_wp-b input sd write-protect signal parallel data capture unit pixclk input image transfer clock pin vsync input vertical synchronization signal pin hsync input horizontal synchronization signal pin pixd0 to pixd7 input 8-bit image data pins pcko output output pin for dot clock realtime clock rtcout output output pin for 1-hz/64-hz clock rtcic0 to rtcic2 input time capture event input pins 12-bit a/d converter an000 to an007, an100 to an120 input input pins for the analog signals to be processed by the a/d converter adtrg0#, adtrg1# input input pins for the ex ternal trigger signals that start the a/d conversion anex0 output extended analog output pin anex1 input extended analog input pin 12-bit d/a converter da0, da1 output output pins fo r the analog signals to be processed by the d/a converter analog power supply avcc0 input analog voltage suppl y pin for the 12-bit a/d converter (unit 0). connect this pin to a branch from the vcc power supply. avss0 input analog ground pin for the 12-bit a/d converter (unit 0). connect this pin to a branch from the vss ground power supply. vrefh0 input analog reference voltage supply pin for the 12-bit a/d converter (unit 0). connect this pin to vcc if the 12-bit a/d converter is not to be used. vrefl0 input analog reference ground pin for the 12-bit a/d converter (unit 0). connect this pin to vss if the 12-bit a/d converter is not to be used. avcc1 input analog voltage supply and reference voltage supply pin for the 12-bit a/d converter (unit 1) and d/a converter. this pin also supplies the analog voltage to the temperature sensor. connect this pin to a branch from the vcc power supply. avss1 input analog voltage supply and reference voltage supply pin for the 12-bit a/d converter (unit 1) and d/a converter. this pin also supplies the analog ground voltage to the temperature sensor. connect this pin to a branch from the vss ground power supply. table 1.4 pin functions (7/8) classifications pin name i/o description
rx64m group 1. overview under development preliminary document specifications in this document are tentative and subject to change. r01ds0173ej0090 rev.0.90 page 25 of 67 feb 28, 2014 i/o ports p00 to p03, p05, p07 i/o 6-bit input/output pins p10 to p17 i/o 8-bit input/output pins p20 to p27 i/o 8-bit input/output pins p30 to p37 i/o 8-bit input/output pins (p35: input pin) p40 to p47 i/o 8-bit input/output pins p50 to p56 i/o 7-bit input/output pins (176-pin devices hav e only p50 to p53) p60 to p67 i/o 8-bit input/output pins p70 to p77 i/o 8-bit input/output pins p80 to p83, p86, p87 i/o 6-bit input/output pins p90 to p97 i/o 8-bit input/output pins pa0 to pa7 i/o 8-bit input/output pins pb0 to pb7 i/o 8-bit input/output pins pc0 to pc7 i/o 8-bit input/output pins pd0 to pd7 i/o 8-bit input/output pins pe0 to pe7 i/o 8-bit input/output pins pf0 to pf5 i/o 6-bit input/output pins pg0 to pg7 i/o 8-bit input/output pins pj3, pj5 i/o 2-bit input/output pins table 1.4 pin functions (8/8) classifications pin name i/o description
rx64m group 1. overview under development preliminary document specifications in this document are tentative and subject to change. r01ds0173ej0090 rev.0.90 page 26 of 67 feb 28, 2014 1.5 pin assignments figure 1.3 to figure 1.9 show the pin assignments. table 1.5 to table 1.10 show the lists of pins and pin functions. figure 1.3 pin assignment (177-pin tflga) abcdefghjklmnpr 15 pe2 pe3 p70 p65 p67 vss vcc pg7 pa6 pb0 p72 pb4 vss vcc pc1 15 14 pe1 pe0 vss pe7 pg3 pa0 pa1 pa2 pa7 vcc pb1 pb5 p73 p75 p74 14 13 p63 p64 pe4 vcc pg2 pg4 pg6 pa3 vss p71 pb3 pb7 pc0 pc2 p76 13 12 p60 vss p62 pe5 pe6 p66 pg5 pa4 pa5 pb2 pb6 p77 pc3 pc4 p80 12 11 pd6 pg1 vcc p61 rx64m group ptlg0177ka-a (177-pin tflga) (upper perspective view) p81 p82 pc6 vcc 11 10 p97 pd4 pg0 pd7 pc5 pc7 p83 vss 10 9 vcc p96 pd3 pd5 p50 p51 p52 p53 9 8p94 pd1 pd2 vss vcc_ usba vss1_ usba p10 p11 8 7 vss p92 pd0 p95 usba_ rref vss2_ usba usba_ dm usba_ dp 7 6vcc p91 p90 p93 avcc_ usba vss_ usb avss_ usba pvss_ usba 6 5 p46 p47 p45 p44 nc vcc_ usb p12 usb0_ dp usb0_ dm 5 4 p42 p41 p43 p00 vss bscanp pf4 p35 pf3 pf1 p25 p86 p15 p14 p13 4 3 vrefl0 p40 vrefh0 p03 pf5 pj3 md/ fined res# p34 pf2 pf0 p24 p22 p87 p16 3 2 avcc0 p07 avcc1 p02 emle vcl xcout vss vcc p32 p30 p26 p23 p17 p20 2 1 avss0 p05 avss1 p01 pj5 vbatt xcin xtal extal p33 p31 p27 vcc vss p21 1 abcdefghjklmnpr note: this figure indicates the power supply pins and i/o port pi ns. for the pin configuration, see table 1.5, list of pin and pin functions (177-pin tflga, 176-pin lfbga).
rx64m group 1. overview under development preliminary document specifications in this document are tentative and subject to change. r01ds0173ej0090 rev.0.90 page 27 of 67 feb 28, 2014 figure 1.4 pin assignment (176-pin lfbga) abcdefghjklmnpr 15 pe2 pe3 p70 p65 p67 vss vcc pg7 pa6 pb0 p72 pb4 vss vcc pc1 15 14 pe1 pe0 vss pe7 pg3 pa0 pa1 pa2 pa7 vcc pb1 pb5 p73 p75 p74 14 13 p63 p64 pe4 vcc pg2 pg4 pg6 pa3 vss p71 pb3 pb7 pc0 pc2 p76 13 12 p60 vss p62 pe5 pe6 p66 pg5 pa4 pa5 pb2 pb6 p77 pc3 pc4 p80 12 11 pd6 pg1 vcc p61 rx64m group plbg0176ga-a (176-pin lfbga) (upper perspective view) p81 p82 pc6 vcc 11 10 p97 pd4 pg0 pd7 pc5 pc7 p83 vss 10 9 vcc p96 pd3 pd5 p50 p51 p52 p53 9 8p94 pd1 pd2 vss vcc_ usba vss1_ usba p10 p11 8 7 vss p92 pd0 p95 usba_ rref vss2_ usba usba_ dm usba_ dp 7 6vcc p91 p90 p93 avcc_ usba vss_ usb avss_ usba pvss_ usba 6 5 p46 p47 p45 p44 vcc_ usb p12 usb0_ dp usb0_ dm 5 4 p42 p41 p43 p00 vss bscanp pf4 p35 pf3 pf1 p25 p86 p15 p14 p13 4 3 vrefl0 p40 vrefh0 p03 pf5 pj3 md/ fined res# p34 pf2 pf0 p24 p22 p87 p16 3 2 avcc0 p07 avcc1 p02 emle vcl xcout vss vcc p32 p30 p26 p23 p17 p20 2 1 avss0 p05 avss1 p01 pj5 vbatt xcin xtal extal p33 p31 p27 vcc vss p21 1 abcdefghjklmnpr note: this figure indicates the power supply pins and i/o port pi ns. for the pin configuration, see table 1.5, list of pin and pin functions (177-pin tflga, 176-pin lfbga).
rx64m group 1. overview under development preliminary document specifications in this document are tentative and subject to change. r01ds0173ej0090 rev.0.90 page 28 of 67 feb 28, 2014 figure 1.5 pin assignment (176-pin lqfp) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 pe0 p64 p63 p62 p61 vss p60 vcc pd7 pg1 pd6 pg0 pd4 p97 pd3 vss p96 vcc pd2 p95 pd1 p94 pd0 p93 p91 p90 p47 p45 p43 p41 p40 p07 pe1 pd5 avcc0 p20 pe3 pe5 vss p70 vcc pe6 pe7 p65 pg2 p66 pg3 p67 pg4 vss pg5 vcc pa1 pg6 pa2 pg7 pa3 pa4 pa5 pa6 pa7 pb0 vcc pb1 pb2 pb4 pb6 p73 pc1 pe4 pa0 vcc avss0 avcc1 p03 avss1 p02 p01 p00 pf5 emle pj5 vss pj3 vcl nc pf4 md/fined xcin xcout res# p37/xtal vss vcc p34 pf2 p30 pf0 p26 vcc vss p23 p21 p36/extal p05 vbatt p32 pe2 p35 p33 pf3 p31 pf1 p27 p25 p24 p22 p17 p87 p16 p86 p15 p14 p13 p12 vcc_usb usb0_dm usb0_dp vss_usb avcc_usba usba_rref avss_usba pvss_usba vss2_usba usba_dp vss1_usba p83 pc7 pc6 pc5 p82 p81 p80 pc4 pc3 p77 usba_dm vcc_usba p11 p10 p53 p52 p51 p50 vss vcc p76 pc2 p75 p74 vss p71 p72 pb3 pb5 pb7 pc0 vss p92 vss vcc p46 p44 p42 vrefh0 vrefl0 note: this figure indicates the power supply pi ns and i/o port pins. for the pin configur ation, see table 1.6, list of pin and p in functions (176-pin lqfp). the 16th pin nc must be connected to vss via a resistor. rx64m group plqp0176kb-a (176-pin lqfp) (top view)
rx64m group 1. overview under development preliminary document specifications in this document are tentative and subject to change. r01ds0173ej0090 rev.0.90 page 29 of 67 feb 28, 2014 figure 1.6 pin assignment (145-pin tflga) abcdefghjklmn 13 pe3 pe4 vss pe6 p67 pa2 pa4 pa7 pb1 pb5 vss vcc p74 13 12 pe1 pe2 p70 pe5 p65 pa1 vcc pb0 pb2 pb6 p73 pc1 p75 12 11 p62 p61 pe0 vcc p66 vss pa6 p71 pb4 pb7 pc2 pc0 pc3 11 10 vss vcc p63 pe7 pa0 pa3 pa5 p72 pb3 p76 pc4 p77 p82 10 9 pd6 pd4 pd7 p64 rx64m group ptlg0145ka-a (145-pin tflga) (upper perspective view) p80 pc5 p81 pc7 9 8 pd2 pd0 pd3 p60 vcc p83 pc6 vss 8 7 p92 p91 pd1 pd5 p51 p52 p50 p55 7 6 p90 p47 vss p93 p53 p56 vss_ usb usb0_ dp 6 5 p45 p43 p46 vcc p44 p54 p13 vcc_ usb usb0_ dm 5 4 p42 vrefl0 p41 p01 emle vbatt bscanp p35 p30 p15 p24 p12 p14 4 3 p40 p05 vrefh0 p03 pj5 pj3 md/ fined vss p32 p31 p16 p86 p87 3 2 p07 avcc0 p02 pf5 vcl xcout res# vcc p33 p26 p23 p17 p20 2 1 avss0 avcc1 avss1 p00 vss xcin xtal extal p34 p27 p25 p22 p21 1 abcdefghjklmn note: this figure indicates the power supply pins and i/o port pi ns. for the pin configuration, see table 1.7, list of pin and pin functions (145-pin tflga).
rx64m group 1. overview under development preliminary document specifications in this document are tentative and subject to change. r01ds0173ej0090 rev.0.90 page 30 of 67 feb 28, 2014 figure 1.7 pin assignment (144-pin lqfp) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 pe0 p64 p63 p62 p61 vss p60 vcc pd7 pd6 pd5 pd4 pd2 pd1 pd0 p93 p92 p91 vss p90 vcc p47 p46 p45 p44 p43 p42 p41 vrefl0 p40 vrefh0 p07 pe1 pd3 avcc0 p74 pc2 p76 p77 pc3 pc4 p80 p81 p82 pc5 pc6 pc7 vcc vss p50 p51 p52 p53 p54 p55 p56 vss_usb usb0_dp usb0_dm vcc_usb p12 p13 p14 p15 p86 p16 p87 p20 p75 p83 p17 pe3 pe5 vss p70 vcc pe6 pe7 p65 p66 p67 pa0 pa1 pa2 vss pa4 vcc pa5 pa6 pa7 pb0 p71 p72 pb1 pb2 pb3 pb4 pb5 pb6 pb7 p73 vss pc0 pc1 pe4 pa3 vcc avss0 avcc1 p03 avss1 p02 p01 p00 pf5 emle pj5 vss pj3 vcl md/fined xcin xcout res# p37/xtal vss p36/extal vcc p35 p34 p32 p31 p30 p27 p26 p25 p24 p23 p21 p05 vbatt p22 p33 pe2 note: this figure indicates the power supply pi ns and i/o port pins. for the pin configuration, see table 1.8, list of pin and p in functions (144-pin lqfp). rx64m group plqp0144ka-a (144-pin lqfp) (top view)
rx64m group 1. overview under development preliminary document specifications in this document are tentative and subject to change. r01ds0173ej0090 rev.0.90 page 31 of 67 feb 28, 2014 figure 1.8 pin assignment (100-pin tflga) rx64m group ptlg0100ja-a (100-pin tflga) (upper perspective view) abcdefghjk 10 pe2 pe3 pe4 pa0 pa3 vss vcc pb7 pc1 pc2 10 9 pe1 pd7 pe5 pa1 pa5 pa7 pb1 pb6 pc0 pc3 9 8 pe0 pd6 pd5 pe7 pa4 pb0 pb4 pc6 pc4 pc5 8 7 pd4 pd3 pd2 pe6 pa6 pb2 pb5 pc7 p50 p51 7 6 pd0 pd1 p47 p46 pa2 pb3 p52 p54 vcc_ usb usb0_ dp 6 5 p43 p44 p42 p45 p41 p12 p53 p55 vss_ usb usb0_ dm 5 4 vrefl0 p40 vrefh0 vbatt p34 p32 p27 p15 p13 p14 4 3 p07 avcc0 pj3 md/ fined res# p35 p30 p16 p17 p20 3 2 avcc1 avss0 avss1 xcout vss vcc p31 p25 p21 p22 2 1 p05 emle vcl xcin xtal extal p33 p26 p24 p23 1 abcdefghjk note: this figure indicates the power supply pins and i/o port pi ns. for the pin configuration, see table 1.9, list of pin and pin functions (100-pin tflga).
rx64m group 1. overview under development preliminary document specifications in this document are tentative and subject to change. r01ds0173ej0090 rev.0.90 page 32 of 67 feb 28, 2014 figure 1.9 pin assignment (100-pin lqfp) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 pe0 pd7 pd6 pd5 pd4 pd3 pd2 pd1 pd0 p47 p46 p45 p43 p42 p41 vrefl0 p40 vrefh0 avcc0 p07 avss0 pe1 p44 pc2 pc4 pc5 pc6 pc7 p50 p51 p52 p53 p54 p55 vss_usb usb0_dp vcc_usb p12 p13 p14 p15 p16 p17 p20 p21 p22 pc3 usb0_dm pe3 pe5 pe6 pe7 pa0 pa1 pa2 pa3 pa4 pa5 pa6 pa7 vss vcc pb1 pb2 pb3 pb4 pb5 pb6 pb7 pc0 pc1 pe4 pb0 avcc1 avss1 pj3 vcl vbatt md/fined xcin xcout res# p37/xtal vss p36/extal p35 p34 p33 p32 p31 p30 p27 p26 p25 p23 emle vcc pe2 p05 p24 note: this figure indicates the power supply pins and i/o port pins. for the pin configuration, see table 1.10, list of pin a nd pin functions (100-pin lqfp). rx64m group plqp0100kb-a (100-pin lqfp) (top view)
rx64m group 1. overview under development preliminary document specifications in this document are tentative and subject to change. r01ds0173ej0090 rev.0.90 page 33 of 67 feb 28, 2014 table 1.5 list of pin and pin function s (177-pin tflga, 176-pin lfbga) (1/7) pin number power supply clock system control i/o port bus exdmac sdramc timer communication memory interface camera interface interrupt s12adc, r12da 177-pin tflga 176-pin lfbga (mtu, gpta, tpu, tmr, ppg, rtc, cmtw, poe, cac) (etherc, scig, scih, rspi, riic, can, usb, ssi) (qspi, sdhi, mmcif, pdc) a1 avss0 a2 avcc0 a3 vrefl0 a4 p42 irq10- ds an002 a5 p46 irq14- ds an006 a6 vcc a7 vss a8 p94 a20/d20 et1_erxd0/ rmii1_rxd0 a9 vcc a10 p97 a23/d23 et1_erxd3 a11 pd6 d6[a6/d6] mtic5v/mtioc8a/ poe4# mmc_d0-b/ sdhi_d0-b/ qio0-b/ qmo-b irq6 an106 a12 p60 cs0# et1_tx_en/ rmii1_txd_en a13 p63 cs3#/cas# a14 pe1 d9[a9/d9] mtioc4c/mtioc3b/ gtioc1b-a/po18 txd12/smosi12/ ssda12/txdx12/ siox12 mmc_d5-b anex1 a15 pe2 d10[a10/d10] mtioc4a/ gtioc0b-a/po23/ tic3 rxd12/smiso12/ sscl12/ rxdx12 mmc_d6-b irq7-ds an100 b1 p05 irq13 da1 b2 p07 irq15 adtrg0# b3 p40 irq8-ds an000 b4 p41 irq9-ds an001 b5 p47 irq15- ds an007 b6 p91 a17/d17 et1_col/sck7 an115 b7 p92 a18/d18 poe4# et1_crs/ rmii1_crs_dv/ rxd7/smiso7/sscl7 an116 b8 pd1 d1[a1/d1] mtioc4b/ gtioc1a-e/poe0# ctx0 irq1 an109 b9 p96 a22/d22 et1_erxd2 b10 pd4 d4[a4/d4] mtioc8b/poe11# mmc_cmd-b/ sdhi_cmd-b/ qssl-b irq4 an112 b11 pg1 d25 et1_rx_er/ rmii1_rx_er b12 vss b13 p64 cs4#/we# b14 pe0 d8[a8/d8] mtioc3d/ gtioc2b-a sck12 mmc_d4-b anex0 b15 pe3 d11[a11/d11] mtioc4b/ gtioc2a-a/po26/ poe8#/toc3 cts12#/rts12#/ ss12#/ et0_erxd3 mmc_d7-b an101 c1 avss1 c2 avcc1 c3 vrefh0
rx64m group 1. overview under development preliminary document specifications in this document are tentative and subject to change. r01ds0173ej0090 rev.0.90 page 34 of 67 feb 28, 2014 c4 p43 irq11-ds an003 c5 p45 irq13- ds an005 c6 p90 a16/d16 et1_rx_dv/ txd7/smosi7/ssda7 an114 c7 pd0 d0[a0/d0] gtioc1b-e/poe4# irq0 an108 c8 pd2 d2[a2/d2] mtioc4d/ gtioc0b-e/tic2 crx0 mmc_d2-b/ sdhi_d2-b/ qio2_b irq2 an110 c9 pd3 d3[a3/d3] mtioc8d/ gtioc0a-e/poe8#/ toc2 mmc_d3-b/ sdhi_d3-b/ qio3-b irq3 an111 c10 pg0 d24 et1_rx_clk/ ref50ck1 c11 vcc c12 p62 cs2#/ras# c13 pe4 d12[a12/d12] mtioc4d/mtioc1a/ gtioc1a-a/po28 et0_erxd2 an102 c14 vss c15 p70 sdclk d1 p01 tmci0 rxd6/smiso6/ sscl6 irq9 an119 d2 p02 tmci1 sck6 irq10 an120 d3 p03 irq11 da0 d4 p00 tmri0 txd6/smosi6/ ssda6 irq8 an118 d5 p44 irq12- ds an004 d6 p93 a19/d19 poe0# et1_linksta/cts7#/ rts7#/ss7# an117 d7 p95 a21/d21 et1_erxd1/ rmii1_rxd1 d8 vss d9 pd5 d5[a5/d5] mtic5w/mtioc8c/ poe10# mmc_clk-b/ sdhi_clk-b/ qspclk-b irq5 an113 d10 pd7 d7[a7/d7] mtic5u/poe0# mmc_d1-b/ sdhi_d1-b/ qio1-b/qmi-b irq7 an107 d11 p61 cs1#/sdcs# d12 pe5 d13[a13/d13] mtioc4c/mtioc2b/ gtioc0a-a et0_rx_clk/ ref50ck0 irq5 an103 d13 vcc d14 pe7 d15[a15/d15] mtioc6a/ gtioc3a-e/toc1 mmc_res#-b/ sdhi_wp-b irq7 an105 d15 p65 cs5#/cke e1 pj5 poe8# cts2#/rts2#/ss2# e2 emle e3 pf5 irq4 e4 vss e5* 1 e12 pe6 d14[a14/d14] mtioc6c/ gtioc3b-e/tic1 mmc_cd-b/ sdhi_cd-b irq6 an104 e13 trdata0 pg2 d26 et1_tx_clk table 1.5 list of pin and pin function s (177-pin tflga, 176-pin lfbga) (2/7) pin number power supply clock system control i/o port bus exdmac sdramc timer communication memory interface camera interface interrupt s12adc, r12da 177-pin tflga 176-pin lfbga (mtu, gpta, tpu, tmr, ppg, rtc, cmtw, poe, cac) (etherc, scig, scih, rspi, riic, can, usb, ssi) (qspi, sdhi, mmcif, pdc)
rx64m group 1. overview under development preliminary document specifications in this document are tentative and subject to change. r01ds0173ej0090 rev.0.90 page 35 of 67 feb 28, 2014 e14 trdata1 pg3 d27 et1_etxd0/ rmii1_txd0 e15 p67 cs7#/dqm1 mtioc7c/ gtioc1b-c crx2 irq15 f1 vbatt f2 vcl f3 pj3 edack1 mtioc3c et0_exout/ cts6#/rts6#/ cts0#/rts0#/ ss6#/ss0# f4 bscanp f12 p66 cs6#/dqm0 mtioc7d/ gtioc2b-c ctx2 f13 trsync pg4 d28 et1_etxd1/ rmii1_txd1 f14 pa0 a0/bc0#/ dqm2 mtioc4a/mtioc6d/ gtioc0b-c/tioca0/ cacref/po16 ssla1-b/ et0_tx_en/ rmii0_txd_en f15 vss g1 xcin g2 xcout g3 md/fined g4 trst# pf4 g12 trclk pg5 d29 et1_etxd2 g13 trdata2 pg6 d30 et1_etxd3 g14 pa1 a1/dqm3 mtioc0b/mtclkc/ mtioc7b/ gtioc2a-c/tiocb0/ po17 sck5/ssla2-b/ et0_wol irq11 g15 vcc h1 xtal p37 h2 vss h3 res# h4 upsel p35 nmi h12 pa4 a4 mtic5u/mtclka/ tioca1/tmri0/po20 txd5/smosi5/ ssda5/ssla0-b/ et0_mdc irq5-ds h13 pa3 a3 mtioc0d/mtclkd/ tiocd0/tclkb/po19 rxd5/smiso5/ sscl5/ et0_mdio irq6-ds h14 pa2 a2 mtioc7a/ gtioc1a-c/po18 rxd5/smiso5/ sscl5/ssla3-b h15 trdata3 pg7 d31 et1_tx_er j1 extal p36 j2 vcc j3 p34 mtioc0a/tmci3/ po12/poe10# sck6/sck0/ et0_linksta irq4 j4 tms pf3 j12 pa5 a5 mtioc6b/ gtioc0a-c/tiocb1/ po21 rspcka-b/ et0_linksta j13 vss j14 pa7 a7 tiocb2/po23 misoa-b/ et0_wol table 1.5 list of pin and pin function s (177-pin tflga, 176-pin lfbga) (3/7) pin number power supply clock system control i/o port bus exdmac sdramc timer communication memory interface camera interface interrupt s12adc, r12da 177-pin tflga 176-pin lfbga (mtu, gpta, tpu, tmr, ppg, rtc, cmtw, poe, cac) (etherc, scig, scih, rspi, riic, can, usb, ssi) (qspi, sdhi, mmcif, pdc)
rx64m group 1. overview under development preliminary document specifications in this document are tentative and subject to change. r01ds0173ej0090 rev.0.90 page 36 of 67 feb 28, 2014 j15 pa6 a6 mtic5v/mtclkb/ gtetrg-c/tioca2/ tmci3/po22/poe10# cts5#/rts5#/ss5#/ mosia-b/ et0_exout k1 p33 edreq1 mtioc0d/tiocd0/ tmri3/po11/poe4#/ poe11# rxd6/rxd0/ smiso6/ smiso0/sscl6/ sscl0/crx0 pcko irq3-ds k2 p32 mtioc0c/tiocc0/ tmo3/po10/ rtcout/rtcic2/ poe0#/poe10# txd6/txd0/ smosi6/smosi0/ ssda6/ssda0/ ctx0/ usb0_vbusen vsync irq2-ds k3 tdi pf2 rxd1/smiso1/ sscl1 k4 tck/finec pf1 sck1 k12 pb2 a10 tiocc3/tclkc/ po26 cts4#/rts4#/cts6#/ rts6#/ss4#/ss6#/ et0_rx_clk/ ref50ck0 k13 p71 a18/cs1# et0_mdio k14 vcc k15 pb0 a8 mtic5w/tioca3/ po24 rxd4/rxd6/smiso4/ smiso6/sscl4/ sscl6/et0_erxd1/ rmii0_rxd1 irq12 l1 p31 mtioc4d/tmci2/ po9/rtcic1 cts1#/rts1#/ ss1#/et1_mdc irq1-ds l2 p30 mtioc4b/tmri3/ po8/rtcic0/poe8# rxd1/smiso1/ sscl1/ et1_mdio irq0-ds l3 tdo pf0 txd1/smosi1/ ssda1 l4 p25 cs5#/ edack1 mtioc4c/mtclkb/ tioca4/po5 rxd3/smiso3/ sscl3/ ssidata1 hsync adtrg0# l12 pb6 a14 mtioc3d/tioca5/ po30 rxd9/et0_etxd1/ rmii0_txd1 l13 pb3 a11 mtioc0a/mtioc4a/ tiocd3/tclkd/ tmo0/po27/poe11# sck4/sck6/ et0_rx_er/ rmii0_rx_er l14 pb1 a9 mtioc0c/mtioc4c/ tiocb3/tmci0/po25 txd4/txd6/smosi4/ smosi6/ssda4/ ssda6/et0_erxd0/ rmii0_rxd0 irq4-ds l15 p72 a19/cs2# et0_mdc m1 p27 cs7# mtioc2b/tmci3/po7 sck1/et1_wol m2 p26 cs6# mtioc2a/tmo1/po6 txd1/cts3#/ rts3#/smosi1/ ss3#/ssda1/ et1_exout m3 p24 cs4#/ edreq1 mtioc4a/mtclka/ tiocb4/tmri1/po4 sck3/ usb0_vbusen/ ssisck1 pixclk m4 p86 mtioc4d/ gtioc2b-b/tioca0 rxd10 pixd1 m5 vcc_usb p12 wr3#/bc3# mtic5u/tmci1 rxd2/smiso2/ sscl2/ scl0[fm+] irq2 m6 avcc_ usba table 1.5 list of pin and pin function s (177-pin tflga, 176-pin lfbga) (4/7) pin number power supply clock system control i/o port bus exdmac sdramc timer communication memory interface camera interface interrupt s12adc, r12da 177-pin tflga 176-pin lfbga (mtu, gpta, tpu, tmr, ppg, rtc, cmtw, poe, cac) (etherc, scig, scih, rspi, riic, can, usb, ssi) (qspi, sdhi, mmcif, pdc)
rx64m group 1. overview under development preliminary document specifications in this document are tentative and subject to change. r01ds0173ej0090 rev.0.90 page 37 of 67 feb 28, 2014 m7 usba_ rref p11 mtic5v/tmci3 sck2/usba_vbus/ usba_vbusen irq1 m8 vcc_ usba p10 ale mtic5w/tmri3 usba_ovrcura irq0 m9 p50 wr0#/wr# txd2/smosi2/ssda2 m10 pc5 a21/cs2#/ wait# mtioc3b/mtclkd/ gtioc1a-d/tmri2/ po29 sck8/rspcka-a/ rts8#/et0_etxd2 mmc_d5-a m11 p81 edack0 mtioc3d/ gtioc0b-d/po27 rxd10/et0_etxd0/ rmii0_txd0 mmc_d3-a/ sdhi_cd-a/ qio3-a m12 p77 cs7# po23 txd11/et0_rx_er/ rmii0_rx_er mmc_clk-a/ sdhi_clk-a/ qspclk-a m13 pb7 a15 mtioc3b/tiocb5/ po31 txd9/et0_crs/ rmii0_crs_dv m14 pb5 a13 mtioc2a/mtioc1b/ tiocb4/tmri1/po29/ poe4# sck9/rts9#/ et0_etxd0/ rmii0_txd0 m15 pb4 a12 tioca4/po28 cts9#/et0_tx_en/ rmii0_txd_en n1 vcc n2 p23 edack0 mtioc3d/mtclkd/ gtioc0a-b/tiocd3/ po3 txd3/cts0#/ rts0#/smosi3/ ss0#/ssda3/ ssisck0 pixd7 n3 p22 edreq0 mtioc3b/mtclkc/ gtioc1a-b/tiocc3/ tmo0/po2 sck0/ usb0_ovrcurb/ usba_ovrcurb/ audio_mclk pixd6 n4 p15 mtioc0b/mtclkb/ gtetrg-b/tiocb2/ tclkb/tmci2/po13 rxd1/sck3/ smiso1/sscl1/ crx1-ds/ usba_vbusen/ ssiws1 pixd0 irq5 n5 p12 wr3#/bc3# mtic5u/tmci1 rxd2/smiso2/ sscl2/ scl0[fm+] irq2 n6 vss_usb n7 vss2_ usba n8 vss1_ usba n9 p51 wr1#/bc1#/ wait# sck2 n10 ub pc7 a23/cs0# mtioc3a/mtclkb/ gtioc3a-d/tmo2/ toc0/po31/cacref txd8/misoa-a/ et0_col mmc_d7-a irq14 n11 p82 edreq1 mtioc4a/ gtioc2a-d/po28 txd10/et0_etxd1/ rmii0_txd1 mmc_d4-a n12 pc3 a19 mtioc4d/ gtioc1b-d/tclkb/ po24 txd5/smosi5/ ssda5/ et0_tx_er mmc_d0-a/ sdhi_d0-a/ qio0-a/ qmo-a n13 pc0 a16 mtioc3c/tclkc/ po17 cts5#/rts5#/ss5#/ ssla1-a/et0_erxd3 irq14 n14 p73 cs3# po16 et0_wol n1 5 vss p1 vs s table 1.5 list of pin and pin function s (177-pin tflga, 176-pin lfbga) (5/7) pin number power supply clock system control i/o port bus exdmac sdramc timer communication memory interface camera interface interrupt s12adc, r12da 177-pin tflga 176-pin lfbga (mtu, gpta, tpu, tmr, ppg, rtc, cmtw, poe, cac) (etherc, scig, scih, rspi, riic, can, usb, ssi) (qspi, sdhi, mmcif, pdc)
rx64m group 1. overview under development preliminary document specifications in this document are tentative and subject to change. r01ds0173ej0090 rev.0.90 page 38 of 67 feb 28, 2014 p2 p17 mtioc3a/mtioc3b/ mtioc4b/ gtioc0b-b/tiocb0/ tclkd/tmo1/po15/ poe8# sck1/txd3/ smosi3/ssda3/ sda2-ds/ ssitxd0 pixd3 irq7 adtrg1# p3 p87 mtioc4c/ gtioc1b-b/tioca2 txd10 pixd2 p4 p14 mtioc3a/mtclka/ tiocb5/tclka/ tmri2/po15 cts1#/rts1#/ ss1#/ctx1/ usb0_ovrcura irq4 p5 usb0_dp p6 avss_ usba p7 usba_dm p8 p10 ale mtic5w/tmri3 usba_ovrcura irq0 p9 p52 rd# rxd2/smiso2/ sscl2 p10 p83 edack1 mtioc4c/ gtioc0a-d cts10#/et0_crs/ rmii0_crs_dv/ sck10 p11 pc6 a22/cs1# mtioc3c/mtclka/ gtioc3b-d/tmci2/ tic0/po30 rxd8/mosia-a/ et0_etxd3 mmc_d6-a irq13 p12 pc4 a20/cs3# mtioc3d/mtclkc/ gtetrg-d/tmci1/ po25/poe0# sck5/cts8#/ssla0- a/et0_tx_clk mmc_d1-a/ sdhi_d1-a/ qio1-a/qmi-a p13 pc2 a18 mtioc4b/ gtioc2b-d/tclka/ po21 rxd5/smiso5/ sscl5/ssla3-a/ et0_rx_dv/ mmc_cd-a/ sdhi_d3-a p14 p75 cs5# po20 sck11/rts11/ et0_erxd0/ rmii0_rxd0/ mmc_res#-a/ sdhi_d2-a p15 vcc r1 p21 mtioc1b/mtioc4a/ gtioc2a-b/tioca3/ tmci0/po1 rxd0/smiso0/ sscl0/ usb0_exicen/ usba_exicen/ ssiws0 pixd5 irq9 r2 p20 mtioc1a/tiocb3/ tmri0/po0 txd0/smosi0/ ssda0/usb0_id/ usba_id/ ssirxd0 pixd4 irq8 r3 p16 mtioc3c/mtioc3d/ tiocb1/tclkc/ tmo2/po14/ rtcout txd1/rxd3/ smosi1/smiso3/ ssda1/sscl3/ scl2-ds/ usb0_vbus/ usb0_vbusen/ usb0_ovrcurb irq6 adtrg0# r4 p13 wr2#/bc2# mtioc0b/tioca5/ tmo3/po13 txd2/smosi2/ ssda2/ sda0[fm+] irq3 adtrg1# r5 usb0_dm r6 pvss_ usba r7 usba_dp r8 p11 mtic5v/tmci3 sck2/ usba_vbus/ usba_vbusen r9 p53* 2 bclk r10 vss table 1.5 list of pin and pin function s (177-pin tflga, 176-pin lfbga) (6/7) pin number power supply clock system control i/o port bus exdmac sdramc timer communication memory interface camera interface interrupt s12adc, r12da 177-pin tflga 176-pin lfbga (mtu, gpta, tpu, tmr, ppg, rtc, cmtw, poe, cac) (etherc, scig, scih, rspi, riic, can, usb, ssi) (qspi, sdhi, mmcif, pdc)
rx64m group 1. overview under development preliminary document specifications in this document are tentative and subject to change. r01ds0173ej0090 rev.0.90 page 39 of 67 feb 28, 2014 note 1. the 176-pin lfbga does not include the e5 pin. note 2. the bclk function is multiplexed with the i/o port functi on for pin p53, so the port function is not available if the ex ternal bus is enabled. r11 vcc r12 p80 edreq0 mtioc3b/po26 sck10/rts10#/ et0_tx_en/ rmii0_txd_en mmc_d2-a/ sdhi_wp-a/ qio2-a r13 p76 cs6# po22 rxd11/et0_rx_clk/ ref50ck0 mmc_cmd-a/ sdhi_cmd-a/ qssl-a r14 p74 a20/cs4# po19 cts11#/et0_erxd1/ rmii0_rxd1 r15 pc1 a17 mtioc3a/tclkd/ po18 sck5/ssla2-a/ et0_erxd2 irq12 table 1.5 list of pin and pin function s (177-pin tflga, 176-pin lfbga) (7/7) pin number power supply clock system control i/o port bus exdmac sdramc timer communication memory interface camera interface interrupt s12adc, r12da 177-pin tflga 176-pin lfbga (mtu, gpta, tpu, tmr, ppg, rtc, cmtw, poe, cac) (etherc, scig, scih, rspi, riic, can, usb, ssi) (qspi, sdhi, mmcif, pdc)
rx64m group 1. overview under development preliminary document specifications in this document are tentative and subject to change. r01ds0173ej0090 rev.0.90 page 40 of 67 feb 28, 2014 table 1.6 list of pin and pin functions (176-pin lqfp) (1/7) pin number power supply clock system control i/o port bus exdmac sdramc timer communication memory interface camera interface interrupt s12adc, r12da 176-pin lqfp (mtu, gpta, tpu, tmr, ppg, rtc, cmtw, poe, cac) (etherc, scig, scih, rspi, riic, can, usb, ssi) (qspi, sdhi, mmcif, pdc) 1 avss0 2p 0 5 irq13 da1 3 avcc1 4p 0 3 irq11 da0 5 avss1 6 p02 tmci1 sck6 irq10 an120 7 p01 tmci0 rxd6/smiso6/ sscl6 irq9 an119 8 p00 tmri0 txd6/smosi6/ ssda6 irq8 an118 9p f 5 irq4 10 emle 11 pj5 poe8# cts2#/rts2#/ss2# 12 vss 13 pj3 edack1 mtioc3c et0_exout/ cts6#/rts6#/ cts0#/rts0#/ ss6#/ss0# 14 vcl 15 vbatt 16 nc 17 trst# pf4 18 md/fined 19 xcin 20 xcout 21 res# 22 xtal p37 23 vss 24 extal p36 25 vcc 26 upsel p35 nmi 27 p34 mtioc0a/tmci3/ po12/poe10# sck6/sck0/ et0_linksta irq4 28 p33 edreq1 mtioc0d/tiocd0/ tmri3/po11/poe4#/ poe11# rxd6/rxd0/ smiso6/ smiso0/sscl6/ sscl0/crx0 pcko irq3-ds 29 p32 mtioc0c/tiocc0/ tmo3/po10/ rtcout/rtcic2/ poe0#/poe10# txd6/txd0/ smosi6/smosi0/ ssda6/ssda0/ ctx0/ usb0_vbusen vsync irq2-ds 30 tms pf3 31 tdi pf2 rxd1/smiso1/ sscl1 32 p31 mtioc4d/tmci2/ po9/rtcic1 cts1#/rts1#/ ss1#/et1_mdc irq1-ds 33 p30 mtioc4b/tmri3/ po8/rtcic0/poe8# rxd1/smiso1/ sscl1/ et1_mdio irq0-ds 34 tck/finec pf1 sck1 35 tdo pf0 txd1/smosi1/ ssda1
rx64m group 1. overview under development preliminary document specifications in this document are tentative and subject to change. r01ds0173ej0090 rev.0.90 page 41 of 67 feb 28, 2014 36 p27 cs7# mtioc2b/tmci3/po7 sck1/et1_wol 37 p26 cs6# mtioc2a/tmo1/po6 txd1/cts3#/ rts3#/smosi1/ ss3#/ssda1/ et1_exout 38 p25 cs5#/ edack1 mtioc4c/mtclkb/ tioca4/po5 rxd3/smiso3/ sscl3/ ssidata1 hsync adtrg0# 39 vcc 40 p24 cs4#/ edreq1 mtioc4a/mtclka/ tiocb4/tmri1/po4 sck3/ usb0_vbusen/ ssisck1 pixclk 41 vss 42 p23 edack0 mtioc3d/mtclkd/ gtioc0a-b/tiocd3/ po3 txd3/cts0#/ rts0#/smosi3/ ss0#/ssda3/ ssisck0 pixd7 43 p22 edreq0 mtioc3b/mtclkc/ gtioc1a-b/tiocc3/ tmo0/po2 sck0/ usb0_ovrcurb/ usba_ovrcurb/ audio_mclk pixd6 44 p21 mtioc1b/mtioc4a/ gtioc2a-b/tioca3/ tmci0/po1 rxd0/smiso0/ sscl0/ usb0_exicen/ usba_exicen/ ssiws0 pixd5 irq9 45 p20 mtioc1a/tiocb3/ tmri0/po0 txd0/smosi0/ ssda0/usb0_id/ usba_id/ ssirxd0 pixd4 irq8 46 p17 mtioc3a/mtioc3b/ mtioc4b/ gtioc0b-b/tiocb0/ tclkd/tmo1/po15/ poe8# sck1/txd3/ smosi3/ssda3/ sda2-ds/ ssitxd0 pixd3 irq7 adtrg1# 47 p87 mtioc4c/ gtioc1b-b/tioca2 txd10 pixd2 48 p16 mtioc3c/mtioc3d/ tiocb1/tclkc/ tmo2/po14/ rtcout txd1/rxd3/ smosi1/smiso3/ ssda1/sscl3/ scl2-ds/ usb0_vbus/ usb0_vbusen/ usb0_ovrcurb irq6 adtrg0# 49 p86 mtioc4d/ gtioc2b-b/tioca0 rxd10 pixd1 50 p15 mtioc0b/mtclkb/ gtetrg-b/tiocb2/ tclkb/tmci2/po13 rxd1/sck3/ smiso1/sscl1/ crx1-ds/ usba_vbusen/ ssiws1 pixd0 irq5 51 p14 mtioc3a/mtclka/ tiocb5/tclka/ tmri2/po15 cts1#/rts1#/ ss1#/ctx1/ usb0_ovrcura irq4 52 p13 wr2#/bc2# mtioc0b/tioca5/ tmo3/po13 txd2/smosi2/ ssda2/ sda0[fm+] irq3 adtrg1# 53 p12 wr3#/bc3# mtic5u/tmci1 rxd2/smiso2/ sscl2/ scl0[fm+] irq2 54 vcc_usb 55 usb0_dm 56 usb0_dp table 1.6 list of pin and pin functions (176-pin lqfp) (2/7) pin number power supply clock system control i/o port bus exdmac sdramc timer communication memory interface camera interface interrupt s12adc, r12da 176-pin lqfp (mtu, gpta, tpu, tmr, ppg, rtc, cmtw, poe, cac) (etherc, scig, scih, rspi, riic, can, usb, ssi) (qspi, sdhi, mmcif, pdc)
rx64m group 1. overview under development preliminary document specifications in this document are tentative and subject to change. r01ds0173ej0090 rev.0.90 page 42 of 67 feb 28, 2014 57 vss_usb 58 avcc_ usba 59 usba_ rref 60 avss_ usba 61 pvss_ usba 62 vss2_ usba 63 usba_dm 64 usba_dp 65 vss1_ usba 66 vcc_ usba 67 p11 mtic5v/tmci3 sck2/usba_vbus/ usba_vbusen irq1 68 p10 ale mtic5w/tmri3 usba_ovrcura irq0 69 p53* 1 bclk 70 p52 rd# rxd2/smiso2/sscl2 71 p51 wr1#/bc1#/ wait# sck2 72 p50 wr0#/wr# txd2/smosi2/ssda2 73 vss 74 p83 edack1 mtioc4c/ gtioc0a-d cts10#/et0_crs/ rmii0_crs_dv/ sck10 75 vcc 76 ub pc7 a23/cs0# mtioc3a/mtclkb/ gtioc3a-d/tmo2/ toc0/po31/cacref txd8/misoa-a/ et0_col mmc_d7-a irq14 77 pc6 a22/cs1# mtioc3c/mtclka/ gtioc3b-d/tmci2/ tic0/po30 rxd8/mosia-a/ et0_etxd3 mmc_d6-a irq13 78 pc5 a21/cs2#/ wait# mtioc3b/mtclkd/ gtioc1a-d/tmri2/ po29 sck8/rspcka-a/ rts8#/et0_etxd2 mmc_d5-a 79 p82 edreq1 mtioc4a/ gtioc2a-d/po28 txd10/et0_etxd1/ rmii0_txd1 mmc_d4-a 80 p81 edack0 mtioc3d/ gtioc0b-d/po27 rxd10/et0_etxd0/ rmii0_txd0 mmc_d3-a/ sdhi_cd-a/ qio3-a 81 p80 edreq0 mtioc3b/po26 sck10/rts10#/ et0_tx_en/ rmii0_txd_en mmc_d2-a/ sdhi_wp-a/ qio2-a 82 pc4 a20/cs3# mtioc3d/mtclkc/ gtetrg-d/tmci1/ po25/poe0# sck5/cts8#/ssla0- a/et0_tx_clk mmc_d1-a/ sdhi_d1-a/ qio1-a/qmi-a 83 pc3 a19 mtioc4d/ gtioc1b-d/tclkb/ po24 txd5/smosi5/ ssda5/ et0_tx_er mmc_d0-a/ sdhi_d0-a/ qio0-a/ qmo-a 84 p77 cs7# po23 txd11/et0_rx_er/ rmii0_rx_er mmc_clk-a/ sdhi_clk-a/ qspclk-a table 1.6 list of pin and pin functions (176-pin lqfp) (3/7) pin number power supply clock system control i/o port bus exdmac sdramc timer communication memory interface camera interface interrupt s12adc, r12da 176-pin lqfp (mtu, gpta, tpu, tmr, ppg, rtc, cmtw, poe, cac) (etherc, scig, scih, rspi, riic, can, usb, ssi) (qspi, sdhi, mmcif, pdc)
rx64m group 1. overview under development preliminary document specifications in this document are tentative and subject to change. r01ds0173ej0090 rev.0.90 page 43 of 67 feb 28, 2014 85 p76 cs6# po22 rxd11/et0_rx_clk/ ref50ck0 mmc_cmd-a/ sdhi_cmd-a/ qssl-a 86 pc2 a18 mtioc4b/ gtioc2b-d/tclka/ po21 rxd5/smiso5/ sscl5/ssla3-a/ et0_rx_dv mmc_cd-a/ sdhi_d3-a 87 p75 cs5# po20 sck11/rts11#/ et0_erxd0/ rmii0_rxd0 mmc_res#-a/ sdhi_d2-a 88 p74 a20/cs4# po19 cts11#/et0_erxd1/ rmii0_rxd1 89 pc1 a17 mtioc3a/tclkd/ po18 sck5/ssla2-a/ et0_erxd2 irq12 90 vcc 91 pc0 a16 mtioc3c/tclkc/ po17 cts5#/rts5#/ss5#/ ssla1-a/et0_erxd3 irq14 92 vss 93 p73 cs3# po16 et0_wol 94 pb7 a15 mtioc3b/tiocb5/ po31 txd9/et0_crs/ rmii0_crs_dv 95 pb6 a14 mtioc3d/tioca5/ po30 rxd9/et0_etxd1/ rmii0_txd1 96 pb5 a13 mtioc2a/mtioc1b/ tiocb4/tmri1/po29/ poe4# sck9/rts9#/ et0_etxd0/ rmii0_txd0 97 pb4 a12 tioca4/po28 cts9#/et0_tx_en/ rmii0_txd_en 98 pb3 a11 mtioc0a/mtioc4a/ tiocd3/tclkd/ tmo0/po27/poe11# sck4/sck6/ et0_rx_er/ rmii0_rx_er 99 pb2 a10 tiocc3/tclkc/ po26 cts4#/rts4#/cts6#/ rts6#/ss4#/ss6#/ et0_rx_clk/ ref50ck0 100 pb1 a9 mtioc0c/mtioc4c/ tiocb3/tmci0/po25 txd4/txd6/smosi4/ smosi6/ssda4/ ssda6/et0_erxd0/ rmii0_rxd0 irq4-ds 101 p72 a19/cs2# et0_mdc 102 p71 a18/cs1# et0_mdio 103 vcc 104 pb0 a8 mtic5w/tioca3/ po24 rxd4/rxd6/smiso4/ smiso6/sscl4/ sscl6/et0_erxd1/ rmii0_rxd1 irq12 105 vss 106 pa7 a7 tiocb2/po23 misoa-b/ et0_wol 107 pa6 a6 mtic5v/mtclkb/ gtetrg-c/tioca2/ tmci3/po22/poe10# cts5#/rts5#/ss5#/ mosia-b/ et0_exout 108 pa5 a5 mtioc6b/ gtioc0a-c/tiocb1/ po21 rspcka-b/ et0_linksta 109 pa4 a4 mtic5u/mtclka/ tioca1/tmri0/po20 txd5/smosi5/ ssda5/ssla0-b/ et0_mdc irq5-ds 110 pa3 a3 mtioc0d/mtclkd/ tiocd0/tclkb/po19 rxd5/smiso5/ sscl5/ et0_mdio irq6-ds table 1.6 list of pin and pin functions (176-pin lqfp) (4/7) pin number power supply clock system control i/o port bus exdmac sdramc timer communication memory interface camera interface interrupt s12adc, r12da 176-pin lqfp (mtu, gpta, tpu, tmr, ppg, rtc, cmtw, poe, cac) (etherc, scig, scih, rspi, riic, can, usb, ssi) (qspi, sdhi, mmcif, pdc)
rx64m group 1. overview under development preliminary document specifications in this document are tentative and subject to change. r01ds0173ej0090 rev.0.90 page 44 of 67 feb 28, 2014 111 trdata3 pg7 d31 et1_tx_er 112 pa2 a2 mtioc7a/ gtioc1a-c/po18 rxd5/smiso5/ sscl5/ssla3-b 113 trdata2 pg6 d30 et1_etxd3 114 pa1 a1/dqm3 mtioc0b/mtclkc/ mtioc7b/ gtioc2a-c/tiocb0/ po17 sck5/ssla2-b/ et0_wol irq11 115 vcc 116 trclk pg5 d29 et1_etxd2 117 vss 118 pa0 a0/bc0#/ dqm2 mtioc4a/mtioc6d/ gtioc0b-c/tioca0/ cacref/po16 ssla1-b/ et0_tx_en/ rmii0_txd_en 119 trsync pg4 d28 et1_etxd1/ rmii1_txd1 120 p67 cs7#/dqm1 mtioc7c/ gtioc1b-c crx2 irq15 121 trdata1 pg3 d27 et1_etxd0/ rmii1_txd0 122 p66 cs6#/dqm0 mtioc7d/ gtioc2b-c ctx2 123 trdata0 pg2 d26 et1_tx_clk 124 p65 cs5#/cke 125 pe7 d15[a15/d15] mtioc6a/ gtioc3a-e/toc1 mmc_res#-b/ sdhi_wp-b irq7 an105 126 pe6 d14[a14/d14] mtioc6c/ gtioc3b-e/tic1 mmc_cd-b/ sdhi_cd-b irq6 an104 127 vcc 128 p70 sdclk 129 vss 130 pe5 d13[a13/d13] mtioc4c/mtioc2b/ gtioc0a-a et0_rx_clk/ ref50ck0 irq5 an103 131 pe4 d12[a12/d12] mtioc4d/mtioc1a/ gtioc1a-a/po28 et0_erxd2 an102 132 pe3 d11[a11/d11] mtioc4b/ gtioc2a-a/po26/ poe8#/toc3 cts12#/rts12#/ ss12#/ et0_erxd3 mmc_d7-b an101 133 pe2 d10[a10/d10] mtioc4a/ gtioc0b-a/po23/ tic3 rxd12/smiso12/ sscl12/ rxdx12 mmc_d6-b irq7-ds an100 134 pe1 d9[a9/d9] mtioc4c/mtioc3b/ gtioc1b-a/po18 txd12/smosi12/ ssda12/txdx12/ siox12 mmc_d5-b anex1 135 pe0 d8[a8/d8] mtioc3d/ gtioc2b-a sck12 mmc_d4-b anex0 136 p64 cs4#/we# 137 p63 cs3#/cas# 138 p62 cs2#/ras# 139 p61 cs1#/sdcs# 140 vss 141 p60 cs0# et1_tx_en/ rmii1_txd_en 142 vcc table 1.6 list of pin and pin functions (176-pin lqfp) (5/7) pin number power supply clock system control i/o port bus exdmac sdramc timer communication memory interface camera interface interrupt s12adc, r12da 176-pin lqfp (mtu, gpta, tpu, tmr, ppg, rtc, cmtw, poe, cac) (etherc, scig, scih, rspi, riic, can, usb, ssi) (qspi, sdhi, mmcif, pdc)
rx64m group 1. overview under development preliminary document specifications in this document are tentative and subject to change. r01ds0173ej0090 rev.0.90 page 45 of 67 feb 28, 2014 143 pd7 d7[a7/d7] mtic5u/poe0# mmc_d1-b/ sdhi_d1-b/ qio1-b/qmi-b irq7 an107 144 pg1 d25 et1_rx_er/ rmii1_rx_er 145 pd6 d6[a6/d6] mtic5v/mtioc8a/ poe4# mmc_d0-b/ sdhi_d0-b/ qio0-b/ qmo-b irq6 an106 146 pg0 d24 et1_rx_clk/ ref50ck1 147 pd5 d5[a5/d5] mtic5w/mtioc8c/ poe10# mmc_clk-b/ sdhi_clk-b/ qspclk-b irq5 an113 148 pd4 d4[a4/d4] mtioc8b/poe11# mmc_cmd-b/ sdhi_cmd-b/ qssl-b irq4 an112 149 p97 a23/d23 et1_erxd3 150 pd3 d3[a3/d3] mtioc8d/ gtioc0a-e/poe8#/ toc2 mmc_d3-b/ sdhi_d3-b/ qio3-b irq3 an111 151 vss 152 p96 a22/d22 et1_erxd2 153 vcc 154 pd2 d2[a2/d2] mtioc4d/ gtioc0b-e/tic2 crx0 mmc_d2-b/ sdhi_d2-b/ qio2_b irq2 an110 155 p95 a21/d21 et1_erxd1/ rmii1_rxd1 156 pd1 d1[a1/d1] mtioc4b/ gtioc1a-e/poe0# ctx0 irq1 an109 157 p94 a20/d20 et1_erxd0/ rmii1_rxd0 158 pd0 d0[a0/d0] gtioc1b-e/poe4# irq0 an108 159 p93 a19/d19 poe0# et1_linksta/cts7#/ rts7#/ss7# an117 160 p92 a18/d18 poe4# et1_crs/ rmii1_crs_dv/ rxd7/smiso7/sscl7 an116 161 p91 a17/d17 et1_col/sck7 an115 162 vss 163 p90 a16/d16 et1_rx_dv/ txd7/smosi7/ssda7 an114 164 vcc 165 p47 irq15- ds an007 166 p46 irq14- ds an006 167 p45 irq13- ds an005 168 p44 irq12- ds an004 169 p43 irq11-ds an003 170 p42 irq10- ds an002 171 p41 irq9-ds an001 172 vrefl0 table 1.6 list of pin and pin functions (176-pin lqfp) (6/7) pin number power supply clock system control i/o port bus exdmac sdramc timer communication memory interface camera interface interrupt s12adc, r12da 176-pin lqfp (mtu, gpta, tpu, tmr, ppg, rtc, cmtw, poe, cac) (etherc, scig, scih, rspi, riic, can, usb, ssi) (qspi, sdhi, mmcif, pdc)
rx64m group 1. overview under development preliminary document specifications in this document are tentative and subject to change. r01ds0173ej0090 rev.0.90 page 46 of 67 feb 28, 2014 note 1. the bclk function is multiplexed with the i/o port functi on for pin p53, so the port function is not available if the ex ternal bus is enabled. 173 p40 irq8-ds an000 174 vrefh0 175 avcc0 176 p07 irq15 adtrg0# table 1.6 list of pin and pin functions (176-pin lqfp) (7/7) pin number power supply clock system control i/o port bus exdmac sdramc timer communication memory interface camera interface interrupt s12adc, r12da 176-pin lqfp (mtu, gpta, tpu, tmr, ppg, rtc, cmtw, poe, cac) (etherc, scig, scih, rspi, riic, can, usb, ssi) (qspi, sdhi, mmcif, pdc)
rx64m group 1. overview under development preliminary document specifications in this document are tentative and subject to change. r01ds0173ej0090 rev.0.90 page 47 of 67 feb 28, 2014 table 1.7 list of pin and pin functions (145-pin tflga) (1/5) pin number power supply clock system control i/o port bus exdmac sdramc timer communication memory interface camera interface interrupt s12adc, r12da 145-pin tflga (mtu, gpta, tpu, tmr, ppg, rtc, cmtw, poe, cac) (etherc, scig, scih, rspi, riic, can, usb, ssi) (qspi, sdhi, mmcif, pdc) a1 avss0 a2 p07 irq15 adtrg0# a3 p40 irq8-ds an000 a4 p42 irq10- ds an002 a5 p45 irq13- ds an005 a6 p90 a16 txd7/smosi7/ssda7 an114 a7 p92 a18 poe4# rxd7/smiso7/sscl7 an116 a8 pd2 d2[a2/d2] mtioc4d/ gtioc0b-e/tic2 crx0 mmc_d2-b/ sdhi_d2-b/ qio2-b irq2 an110 a9 pd6 d6[a6/d6] mtic5v/mtioc8a/ poe4# mmc_d0-b/ sdhi_d0-b/ qio0-b/ qmo-b irq6 an106 a10 vss a11 p62 cs2#/ras# a12 pe1 d9[a9/d9] mtioc4c/mtioc3b/ gtioc1b-a/po18 txd12/smosi12/ ssda12/txdx12/ siox12 mmc_d5-b anex1 a13 pe3 d11[a11/d11] mtioc4b/ gtioc2a-a/po26/ poe8#/toc3 cts12#/rts12#/ ss12#/et0_erxd3/ mmc_d7-b an101 b1 avcc1 b2 avcc0 b3 p05 irq13 da1 b4 vrefl0 b5 p43 irq11-ds an003 b6 p47 irq15- ds an007 b7 p91 a17 sck7 an115 b8 pd0 d0[a0/d0] gtioc1b-e/poe4# irq0 an108 b9 pd4 d4[a4/d4] mtioc8b/poe11# mmc_cmd-b/ sdhi_cmd-b/ qssl-b irq4 an112 b10 vcc b11 p61 cs1#/sdcs# b12 pe2 d10[a10/d10] mtioc4a/ gtioc0b-a/po23/ tic3 rxd12/smiso12/ sscl12/rxdx12/ mmc_d6-b irq7-ds an100 b13 pe4 d12[a12/d12] mtioc4d/mtioc1a/ gtioc1a-a/po28 et0_erxd2 an102 c1 avss1 c2 p02 tmci1 sck6 irq10 an120 c3 vrefh0 c4 p41 irq9-ds an001 c5 p46 irq14- ds an006 c6 vss c7 pd1 d1[a1/d1] mtioc4b/ gtioc1a-e/poe0# ctx0 irq1 an109 c8 pd3 d3[a3/d3] mtioc8d/ gtioc0a-e/poe8#/ toc2 mmc_d3-b/ sdhi_d3-b/ qio3-b irq3 an111
rx64m group 1. overview under development preliminary document specifications in this document are tentative and subject to change. r01ds0173ej0090 rev.0.90 page 48 of 67 feb 28, 2014 c9 pd7 d7[a7/d7] mtic5u/poe0# mmc_d1-b/ sdhi_d1-b/ qio1-b/qmi-b irq7 an107 c10 p63 cs3#/cas# c11 pe0 d8[a8/d8] mtioc3d/ gtioc2b-a sck12 mmc_d4-b anex0 c12 p70 sdclk c13 vss d1 p00 tmri0 txd6/smosi6/ssda6 irq8 an118 d2 pf5 irq4 d3 p03 irq11 da0 d4 p01 tmci0 rxd6/smiso6/sscl6 irq9 an119 d5 vcc d6 p93 a19 poe0# cts7#/rts7#/ss7# an117 d7 pd5 d5[a5/d5] mtic5w/mtioc8c/ poe10# mmc_clk-b/ sdhi_clk-b/ qspclk-b irq5 an113 d8 p60 cs0# d9 p64 cs4#/we# d10 pe7 d15[a15/d15] mtioc6a/ gtioc3a-e/toc1 mmc_res#-b/ sdhi_wp-b irq7 an105 d11 vcc d12 pe5 d13[a13/d13] mtioc4c/mtioc2b/ gtioc0a-a et0_rx_clk/ ref50ck0 irq5 an103 d13 pe6 d14[a14/d14] tioc6c/gtioc3b-e/ tic1 mmc_cd-b/ sdhi_cd-b irq6 an104 e1 vss e2 vcl e3 pj5 poe8# cts2#/rts2#/ss2# e4 emle e5 p44 irq12- ds an004 e10 pa0 a0/bc0# mtioc4a/mtioc6d/ gtioc0b-c/tioca0/ cacref/po16 ssla1-a/ et0_tx_en/ rmii0_txd_en e11 p66 cs6#/dqm0 mtioc7d/ gtioc2b-c ctx2 e12 p65 cs5#/cke e13 p67 cs7#/dqm1 mtioc7c/ gtioc1b-c crx2 irq15 f1 xcin f2 xcout f3 pj3 edack1 mtioc3c et0_exout/cts6#/ rts6#/cts0#/rts0#/ ss6#/ss0# f4 vbatt f10 pa3 a3 mtioc0d/mtclkd/ tiocd0/tclkb/po19 rxd5/smiso5/ sscl5/et0_mdio irq6-ds f11 vss f12 pa1 a1 mtioc0b/mtclkc/ mtioc7b/ gtioc2a-c/tiocb0/ po17 sck5/ssla2-a/ et0_wol irq11 table 1.7 list of pin and pin functions (145-pin tflga) (2/5) pin number power supply clock system control i/o port bus exdmac sdramc timer communication memory interface camera interface interrupt s12adc, r12da 145-pin tflga (mtu, gpta, tpu, tmr, ppg, rtc, cmtw, poe, cac) (etherc, scig, scih, rspi, riic, can, usb, ssi) (qspi, sdhi, mmcif, pdc)
rx64m group 1. overview under development preliminary document specifications in this document are tentative and subject to change. r01ds0173ej0090 rev.0.90 page 49 of 67 feb 28, 2014 f13 pa2 a2 mtioc7a/ gtioc1a-c/po18 rxd5/smiso5/ sscl5/ssla3-a g1 xtal p37 g2 res g3 md/fined g4 bscanp g10 pa5 a5 mtioc6b/tiocb1/ gtioc0a-c/po21 rspcka-b/ et0_linksta g11 pa6 a6 mtic5v/mtclkb/ gtetrg-c/tioca2/ tmci3/po22/poe10# cts5#/rts5#/ss5#/ mosia-b/ et0_exout g12 vcc g13 pa4 a4 mtic5u/mtclka/ tioca1/tmri0/po20 txd5/smosi5/ ssda5/ssla0-a/ et0_mdc irq5-ds h1 extal p36 h2 vcc h3 vss h4 upsel p35 nmi h10 p72 a19/cs2# et0_mdc h11 p71 a18/cs1# et0_mdio h12 pb0 a8 mtic5w/tioca3/ po24 rxd4/rxd6/smiso4/ smiso6/sscl4/ sscl6/et0_erxd1/ rmii0_rxd1 irq12 h13 pa7 a7 tiocb2/po23 misoa-b/et0_wol j1 trst# p34 mtioc0a/tmci3/ po12/poe10# sck6/sck0/ et0_linksta irq4 j2 p33 edreq1 mtioc0d/tiocd0/ tmri3/po11/poe4#/ poe11# rxd6/rxd0/smiso6/ smiso0/sscl6/ sscl0/crx0 pcko irq3-ds j3 p32 mtioc0c/tiocc0/ tmo3/po10/ rtcout/rtcic2/ poe0#/poe10# txd6/txd0/smosi6/ smosi0/ssda6/ ssda0/ctx0/ usb0_vbusen vsync irq2-ds j4 tdi p30 mtioc4b/tmri3/ po8/rtcic0/poe8# rxd1/smiso1/sscl1 irq0-ds j10 pb3 a11 mtioc0a/mtioc4a/ tiocd3/tclkd/ tmo0/po27/poe11# sck4/sck6/ et0_rx_er/ rmii0_rx_er j11 pb4 a12 tioca4/po28 cts9#/et0_tx_en/ rmii0_txd_en j12 pb2 a10 tiocc3/tclkc/ po26 cts4#/rts4#/cts6#/ rts6#/ss4#/ss6#/ et0_rx_clk/ ref50ck0 j13 pb1 a9 mtioc0c/mtioc4c/ tiocb3/tmci0/po25 txd4/txd6/smosi4/ smosi6/ssda4/ ssda6/et0_erxd0/ rmii0_rxd0 irq4-ds k1 tck/finec p27 cs7# mt ioc2b/tmci3/po7 sck1 k2 tdo p26 cs6# mtioc2a/tmo1/po6 txd1/cts3#/rts3#/ smosi1/ss3#/ssda1 k3 tms p31 mtioc4d/tmci2/ po9/rtcic1 cts1#/rts1#/ss1# irq1-ds k4 p15 mtioc0b/mtclkb/ gtetrg-b/tiocb2/ tclkb/tmci2/po13 rxd1/sck3/smiso1/ sscl1/crx1-ds/ ssiws1 pixd0 irq5 table 1.7 list of pin and pin functions (145-pin tflga) (3/5) pin number power supply clock system control i/o port bus exdmac sdramc timer communication memory interface camera interface interrupt s12adc, r12da 145-pin tflga (mtu, gpta, tpu, tmr, ppg, rtc, cmtw, poe, cac) (etherc, scig, scih, rspi, riic, can, usb, ssi) (qspi, sdhi, mmcif, pdc)
rx64m group 1. overview under development preliminary document specifications in this document are tentative and subject to change. r01ds0173ej0090 rev.0.90 page 50 of 67 feb 28, 2014 k5 trdata2 p54 ale/edack0 mtioc4b/tmci1 cts2#/rts2#/ss2#/ ctx1/et0_linksta k6 p53 bclk k7 p51 wr1#/bc1#/ wait# sck2 k8 vcc k9 trdata0 p80 edreq0 mtioc3b/po26 sck10/rts10#/ et0_tx_en/ rmii0_txd_en mmc_d2-a/ sdhi_wp-a/ qio2-a k10 p76 cs6# po22 rxd11/et0_rx_clk/ ref50ck0 mmc_cmd-a/ sdhi_cmd-a/ qssl-a k11 pb7 a15 mtioc3b/tiocb5/ po31 txd9/et0_crs/ rmii0_crs_dv k12 pb6 a14 mtioc3d/tioca5/ po30 rxd9/et0_etxd1/ rmii0_txd1 k13 pb5 a13 mtioc2a/mtioc1b/ tiocb4/tmri1/po29/ poe4# sck9/rts9#/ et0_etxd0/ rmii0_txd0 l1 p25 cs5#/ edack1 mtioc4c/mtclkb/ tioca4/po5 rxd3/smiso3/ sscl3/ssidata1 hsync adtrg0# l2 p23 edack0 mtioc3d/mtclkd/ gtioc0a-b/tiocd3/ po3 txd3/cts0#/rts0#/ smosi3/ss0#/ ssda3/ssisck0 pixd7 l3 p16 mtioc3c/mtioc3d/ tiocb1/tclkc/ tmo2/po14/ rtcout txd1/rxd3/smosi1/ smiso3/ssda1/ sscl3/scl2-ds/ usb0_vbus/ usb0_vbusen/ usb0_ovrcurb irq6 adtrg0# l4 p24 cs4#/ edreq1 mtioc4a/mtclka/ tiocb4/tmri1/po4 sck3/ usb0_vbusen/ ssisck1 pixclk l5 p13 mtioc0b/tioca5/ tmo3/po13 txd2/smosi2/ ssda2/sda0[fm+] irq3 adtrg1# l6 p56 edack1 mtioc3c/tioca1 l7 p52 rd# rxd2/smiso2/sscl2 l8 trclk p83 edack1 mtioc4c/ gtioc0a-d cts10#/et0_crs/ rmii0_crs_dv/ sck10 l9 pc5 a21/cs2#/ wait# mtioc3b/mtclkd/ gtioc1a-d/tmri2/ po29 sck8/rspcka-a/ rts8#/et0_etxd2 mmc_d5-a l10 pc4 a20/cs3# mtioc3d/mtclkc/ gtetrg-d/tmci1/ po25/poe0# sck5/cts8#/ ssla0-a/ et0_tx_clk mmc_d1-a/ sdhi_d1-a/ qio1-a/qmi-a l11 pc2 a18 mtioc4b/ gtioc2b-d/tclka/ po21 rxd5/smiso5/ sscl5/ssla3-a/ et0_rx_dv mmc_cd-a/ sdhi_d3-a l12 p73 cs3# po16 et0_wol l13 vss m1 p22 edreq0 mtioc3b/mtclkc/ gtioc1a-b/tiocc3/ tmo0/po2 sck0/ usb0_ovrcurb/ audio_mclk pi xd6 m2 p17 mti oc3 a/mtioc3b/ mtioc4b/ gtioc0b-b/tiocb0/ tclkd/tmo1/po15/ poe8# sck1/txd3/smosi3/ ssda3/sda2-ds/ ssitxd0 pixd3 irq7 adtrg1# m3 p86 mtioc4d/ gtioc2b-b/tioca0 rxd10 pixd1 table 1.7 list of pin and pin functions (145-pin tflga) (4/5) pin number power supply clock system control i/o port bus exdmac sdramc timer communication memory interface camera interface interrupt s12adc, r12da 145-pin tflga (mtu, gpta, tpu, tmr, ppg, rtc, cmtw, poe, cac) (etherc, scig, scih, rspi, riic, can, usb, ssi) (qspi, sdhi, mmcif, pdc)
rx64m group 1. overview under development preliminary document specifications in this document are tentative and subject to change. r01ds0173ej0090 rev.0.90 page 51 of 67 feb 28, 2014 m4 p12 tmci1 rxd2/smiso2/ sscl2/scl0[fm+] irq2 m5 vcc_usb m6 vss_usb m7 p50 wr0#/wr# txd2/smosi2/ssda2 m8 pc6 a22/cs1# mtioc3c/mtclka/ gtioc3b-d/tmci2/ tic0/po30 rxd8/mosia-a/ et0_etxd3 mmc_d6-a irq13 m9 trdata1 p81 edack0 mtioc3d/ gtioc0b-d/po27 rxd10/et0_etxd0/ rmii0_txd0 mmc_d3-a/ sdhi_cd-a/ qio3-a m10 p77 cs7# po23 txd11/et0_rx_er/ rmii0_rx_er mmc_clk-a/ sdhi_clk-a/ qspclk-a m11 pc0 a16 mtioc3c/tclkc/ po17 cts5#/rts5#/ss5#/ ssla1-a/et0_erxd3 irq14 m12 pc1 a17 mtioc3a/tclkd/ po18 sck5/ssla2-a/ et0_erxd2 irq12 m13 vcc n1 p21 mtioc1b/mtioc4a/ gtioc2a-b/tioca3/ tmci0/po1 rxd0/smiso0/ sscl0/ usb0_exicen/ ssiws0 pixd5 irq9 n2 p20 mtioc1a/tiocb3/ tmri0/po0 txd0/smosi0/ ssda0/usb0_id/ ssirxd0 pixd4 irq8 n3 p87 mtioc4c/ gtioc1b-b/tioca2 txd10 pixd2 n4 p14 mtioc3a/mtclka/ tiocb5/tclka/ tmri2/po15 cts1#/rts1#/ss1#/ ctx1/ usb0_ovrcura irq4 n5 usb0_dm n6 usb0_dp n7 trdata3 p55 wait#/ edreq0 mtioc4d/tmo3 crx1/et0_exout irq10 n8 vss n9 ub pc7 a23/cs0# mtioc3a/mtclkb/ gtioc3a-d/tmo2/ toc0/po31/cacref txd8/misoa-a/ et0_col mmc_d7-a irq14 n10 trsync p82 edreq1 mtioc4a/ gtioc2a-d/po28 txd10/et0_etxd1/ rmii0_txd1 mmc_d4-a n11 pc3 a19 mtioc4d/ gtioc1b-d/tclkb/ po24 txd5/smosi5/ ssda5/et0_tx_er mmc_d0-a/ sdhi_d0-a/ qio0-a/ qmo-a n12 p75 cs5# po20 sck11/rts11#/ et0_erxd0/ rmii0_rxd0 mmc_res#-a/ sdhi_d2-a n13 p74 a20/cs4# po19 cts11#/et0_erxd1/ rmii0_rxd1 table 1.7 list of pin and pin functions (145-pin tflga) (5/5) pin number power supply clock system control i/o port bus exdmac sdramc timer communication memory interface camera interface interrupt s12adc, r12da 145-pin tflga (mtu, gpta, tpu, tmr, ppg, rtc, cmtw, poe, cac) (etherc, scig, scih, rspi, riic, can, usb, ssi) (qspi, sdhi, mmcif, pdc)
rx64m group 1. overview under development preliminary document specifications in this document are tentative and subject to change. r01ds0173ej0090 rev.0.90 page 52 of 67 feb 28, 2014 table 1.8 list of pin and pin functions (144-pin lqfp) (1/5) pin number power supply clock system control i/o port bus exdmac sdramc timer communication memory interface camera interface interrupt s12adc, r12da 144-pin lqfp (mtu, gpta, tpu, tmr, ppg, rtc, cmtw, poe, cac) (etherc, scig, scih, rspi, riic, can, usb, ssi) (qspi, sdhi, mmcif, pdc) 1 avss0 2p 0 5 irq13 da1 3 avcc1 4p 0 3 irq11 da0 5 avss1 6 p02 tmci1 sck6 irq10 an120 7 p01 tmci0 rxd6/smiso6/sscl6 irq9 an119 8 p00 tmri0 txd6/smosi6/ssda6 irq8 an118 9p f 5 irq4 10 emle 11 pj5 poe8# 12 vss 13 pj3 edack1 mtioc3c et0_exout/cts6#/ rts6#/cts0#/rts0#/ ss6#/ss0# 14 vcl 15 vbatt 16 md/fined 17 xcin 18 xcout 19 res 20 xtal p37 21 vss 22 extal p36 23 vcc 24 p35 nmi 25 trst# p34 mtioc0a/tmci3/ po12/poe10# sck6/sck0/ et0_linksta irq4 26 p33 edreq1 mtioc0d/tiocd0/ tmri3/po11/poe4#/ poe11# rxd6/rxd0/smiso6/ smiso0/sscl6/ sscl0/crx0 pcko irq3-ds 27 p32 mtioc0c/tiocc0/ tmo3/po10/ rtcout/rtcic2/ poe0#/poe10# txd6/txd0/smosi6/ smosi0/ssda6/ ssda0/ctx0/ usb0_vbusen vsync irq2-ds 28 tms p31 mtioc4d/tmci2/ po9/rtcic1 cts1#/rts1#/ss1# irq1-ds 29 tdi p30 mtioc4b/tmri3/ po8/rtcic0/poe8# rxd1/smiso1/sscl1 irq0-ds 30 tck/finec p27 cs7# mt ioc2b/tmci3/po7 sck1 31 tdo p26 cs6# mtioc2a/tmo1/po6 txd1/cts3#/rts3#/ smosi1/ss3#/ssda1 32 p25 cs5#/ edack1 mtioc4c/mtclkb/ tioca4/po5 rxd3/smiso3/ sscl3/ssidata1 hsync adtrg0# 33 p24 cs4#/ edreq1 mtioc4a/mtclka/ tiocb4/tmri1/po4 sck3/ usb0_vbusen/ ssisck1 pixclk 34 p23 edack0 mtioc3d/mtclkd/ gtioc0a-b/tiocd3/ po3 txd3/cts0#/rts0#/ smosi3/ss0#/ ssda3/ssisck0 pixd7 35 p22 edreq0 mtioc3b/mtclkc/ gtioc1a-b/tiocc3/ tmo0/po2 sck0/ usb0_ovrcurb/ audio_mclk pixd6
rx64m group 1. overview under development preliminary document specifications in this document are tentative and subject to change. r01ds0173ej0090 rev.0.90 page 53 of 67 feb 28, 2014 36 p21 mtioc1b/mtioc4a/ gtioc2a-b/tioca3/ tmci0/po1 rxd0/smiso0/ sscl0/ usb0_exicen/ ssiws0 pixd5 irq9 37 p20 mtioc1a/tiocb3/ tmri0/po0 txd0/smosi0/ ssda0/usb0_id/ ssirxd0 pixd4 irq8 38 p17 mtioc3a/mtioc3b/ mtioc4b/ gtioc0b-b/tiocb0/ tclkd/tmo1/po15/ poe8# sck1/txd3/smosi3/ ssda3/sda2-ds/ ssitxd0 pixd3 irq7 adtrg1# 39 p87 mtioc4c/ gtioc1b-b/tioca2 txd10 pixd2 40 p16 mtioc3c/mtioc3d/ tiocb1/tclkc/ tmo2/po14/ rtcout txd1/rxd3/smosi1/ smiso3/ssda1/ sscl3/scl2-ds/ usb0_vbus/ usb0_vbusen/ usb0_ovrcurb irq6 adtrg0# 41 p86 mtioc4d/ gtioc2b-b/tioca0 rxd10 pixd1 42 p15 mtioc0b/mtclkb/ gtetrg-b/tiocb2/ tclkb/tmci2/po13 rxd1/sck3/smiso1/ sscl1/crx1-ds/ ssiws1 pixd0 irq5 43 p14 mtioc3a/mtclka/ tiocb5/tclka/ tmri2/po15 cts1#/rts1#/ss1#/ ctx1/ usb0_ovrcura irq4 44 p13 mtioc0b/tioca5/ tmo3/po13 txd2/smosi2/ ssda2/sda0[fm+] irq3 adtrg1# 45 p12 tmci1 rxd2/smiso2/ sscl2/scl0[fm+] irq2 46 vcc_usb 47 usb0_dm 48 usb0_dp 49 vss_usb 50 p56 edack1 mtioc3c/tioca1 51 trdata3 p55 wait#/ edreq0 mtioc4d/tmo3 crx1/et0_exout irq10 52 trdata2 p54 ale/edack0 mtioc4b/tmci1 cts2#/rts2#/ss2#/ ctx1/et0_linksta 53 p53 bclk 54 p52 rd# rxd2/smiso2/sscl2 55 p51 wr1#/bc1#/ wait# sck2 56 p50 wr0#/wr# txd2/smosi2/ssda2 57 vss 58 trclk p83 edack1 mtioc4c/ gtioc0a-d cts10#/et0_crs/ rmii0_crs_dv/ sck10 59 vcc 60 ub pc7 a23/cs0# mtioc3a/mtclkb/ gtioc3a-d/tmo2/ toc0/po31/cacref txd8/misoa-a/ et0_col mmc_d7-a irq14 61 pc6 a22/cs1# mtioc3c/mtclka/ gtioc3b-d/tmci2/ tic0/po30 rxd8/mosia-a/ et0_etxd3 mmc_d6-a irq13 62 pc5 a21/cs2#/ wait# mtioc3b/mtclkd/ gtioc1a-d/tmri2/ po29 sck8/rspcka-a/ rts8#/et0_etxd2 mmc_d5-a table 1.8 list of pin and pin functions (144-pin lqfp) (2/5) pin number power supply clock system control i/o port bus exdmac sdramc timer communication memory interface camera interface interrupt s12adc, r12da 144-pin lqfp (mtu, gpta, tpu, tmr, ppg, rtc, cmtw, poe, cac) (etherc, scig, scih, rspi, riic, can, usb, ssi) (qspi, sdhi, mmcif, pdc)
rx64m group 1. overview under development preliminary document specifications in this document are tentative and subject to change. r01ds0173ej0090 rev.0.90 page 54 of 67 feb 28, 2014 63 trsync p82 edreq1 mtioc4a/ gtioc2a-d/po28 txd10/et0_etxd1/ rmii0_txd1 mmc_d4-a 64 trdata1 p81 edack0 mtioc3d/ gtioc0b-d/po27 rxd10/et0_etxd0/ rmii0_txd0 mmc_d3-a/ sdhi_cd-a/ qio3-a 65 trdata0 p80 edreq0 mtioc3b/po26 sck10/rts10#/ et0_tx_en/ rmii0_txd_en mmc_d2-a/ sdhi_wp-a/ qio2-a 66 pc4 a20/cs3# mtioc3d/mtclkc/ gtetrg-d/tmci1/ po25/poe0# sck5/cts8#/ ssla0-a/ et0_tx_clk/ mmc_d1-a/ sdhi_d1-a/ qio1-a/qmi-a 67 pc3 a19 mtioc4d/ gtioc1b-d/tclkb/ po24 txd5/smosi5/ ssda5/et0_tx_er mmc_d0-a/ sdhi_d0-a/ qio0-a/ qmo-a 68 p77 cs7# po23 txd11/et0_rx_er/ rmii0_rx_er mmc_clk-a/ sdhi_clk-a/ qspclk-a 69 p76 cs6# po22 rxd11/et0_rx_clk/ ref50ck0 mmc_cmd-a/ sdhi_cmd-a/ qssl-a 70 pc2 a18 mtioc4b/ gtioc2b-d/tclka/ po21 rxd5/smiso5/ sscl5/ssla3-a/ et0_rx_dv mmc_cd-a/ sdhi_d3-a 71 p75 cs5# po20 sck11/rts11/ et0_erxd0/ rmii0_rxd0 mmc_res#-a/ sdhi_d2-a 72 p74 a20/cs4# po19 cts11#/et0_erxd1/ rmii0_rxd1 73 pc1 a17 mtioc3a/tclkd/ po18 sck5/ssla2-a/ et0_erxd2 irq12 74 vcc 75 pc0 a16 mtioc3c/tclkc/ po17 cts5#/rts5#/ss5#/ ssla1-a/et0_erxd3 irq14 76 vss 77 p73 cs3# po16 et0_wol 78 pb7 a15 mtioc3b/tiocb5/ po31 txd9/et0_crs/ rmii0_crs_dv 79 pb6 a14 mtioc3d/tioca5/ po30 rxd9/et0_etxd1/ rmii0_txd1 80 pb5 a13 mtioc2a/mtioc1b/ tiocb4/tmri1/po29/ poe4# sck9/rts9#/ et0_etxd0/ rmii0_txd0 81 pb4 a12 tioca4/po28 cts9#/et0_tx_en/ rmii0_txd_en 82 pb3 a11 mtioc0a/mtioc4a/ tiocd3/tclkd/ tmo0/po27/poe11# sck4/sck6/ et0_rx_er/ rmii0_rx_er 83 pb2 a10 tiocc3/tclkc/ po26 cts4#/rts4#/cts6#/ rts6#/ss4#/ss6#/ et0_rx_clk/ ref50ck0 84 pb1 a9 mtioc0c/mtioc4c/ tiocb3/tmci0/po25 txd4/txd6/smosi4/ smosi6/ssda4/ ssda6/et0_erxd0/ rmii0_rxd0 irq4-ds 85 p72 a19/cs2# et0_mdc 86 p71 a18/cs1# et0_mdio table 1.8 list of pin and pin functions (144-pin lqfp) (3/5) pin number power supply clock system control i/o port bus exdmac sdramc timer communication memory interface camera interface interrupt s12adc, r12da 144-pin lqfp (mtu, gpta, tpu, tmr, ppg, rtc, cmtw, poe, cac) (etherc, scig, scih, rspi, riic, can, usb, ssi) (qspi, sdhi, mmcif, pdc)
rx64m group 1. overview under development preliminary document specifications in this document are tentative and subject to change. r01ds0173ej0090 rev.0.90 page 55 of 67 feb 28, 2014 87 pb0 a8 mtic5w/tioca3/ po24 rxd4/rxd6/smiso4/ smiso6/sscl4/ sscl6/et0_erxd1/ rmii0_rxd1 irq12 88 pa7 a7 tiocb2/po23 misoa-b/et0_wol 89 pa6 a6 mtic5v/mtclkb/ gtetrg-c/tioca2/ tmci3/po22/poe10# cts5#/rts5#/ss5#/ mosia-b/ et0_exout 90 pa5 a5 mtioc6b/tiocb1/ gtioc0a-c/po21 rspcka-b/ et0_linksta 91 vcc 92 pa4 a4 mtic5u/mtclka/ tioca1/tmri0/po20 txd5/smosi5/ ssda5/ssla0-a/ et0_mdc irq5-ds 93 vss 94 pa3 a3 mtioc0d/mtclkd/ tiocd0/tclkb/po19 rxd5/smiso5/ sscl5/et0_mdio irq6-ds 95 pa2 a2 mtioc7a/ gtioc1a-c/po18 rxd5/smiso5/ sscl5/ssla3-a 96 pa1 a1 mtioc0b/mtclkc/ mtioc7b/ gtioc2a-c/tiocb0/ po17 sck5/ssla2-a/ et0_wol irq11 97 pa0 a0/bc0# mtioc4a/mtioc6d/ gtioc0b-c/tioca0/ cacref/po16 ssla1-a/ et0_tx_en/ rmii0_txd_en 98 p67 cs7#/dqm1 mtioc7c/ gtioc1b-c crx2 irq15 99 p66 cs6#/dqm0 mtioc7d/ gtioc2b-c ctx2 100 p65 cs5#/cke 101 pe7 d15[a15/d15] mtioc6a/ gtioc3a-e/toc1 mmc_res#-b/ sdhi_wp-b irq7 an105 102 pe6 d14[a14/d14] tioc6c/gtioc3b-e/ tic1 mmc_cd-b/ sdhi_cd-b irq6 an104 103 vcc 104 p70 sdclk 105 vss 106 pe5 d13[a13/d13] mtioc4c/mtioc2b/ gtioc0a-a et0_rx_clk/ ref50ck0 irq5 an103 107 pe4 d12[a12/d12] mtioc4d/mtioc1a/ gtioc1a-a/po28 et0_erxd2 an102 108 pe3 d11[a11/d11] mtioc4b/ gtioc2a-a/po26/ poe8#/toc3 cts12#/rts12#/ ss12#/et0_erxd3/ mmc_d7-b an101 109 pe2 d10[a10/d10] mtioc4a/ gtioc0b-a/po23/ tic3 rxd12/smiso12/ sscl12/rxdx12/ mmc_d6-b irq7-ds an100 110 pe1 d9[a9/d9] mtioc4c/mtioc3b/ gtioc1b-a/po18 txd12/smosi12/ ssda12/txdx12/ siox12 mmc_d5-b anex1 111 pe0 d8[a8/d8] mtioc3d/ gtioc2b-a sck12 mmc_d4-b anex0 112 p64 cs4#/we# 113 p63 cs3#/cas# 114 p62 cs2#/ras# 115 p61 cs1#/sdcs# 116 vss table 1.8 list of pin and pin functions (144-pin lqfp) (4/5) pin number power supply clock system control i/o port bus exdmac sdramc timer communication memory interface camera interface interrupt s12adc, r12da 144-pin lqfp (mtu, gpta, tpu, tmr, ppg, rtc, cmtw, poe, cac) (etherc, scig, scih, rspi, riic, can, usb, ssi) (qspi, sdhi, mmcif, pdc)
rx64m group 1. overview under development preliminary document specifications in this document are tentative and subject to change. r01ds0173ej0090 rev.0.90 page 56 of 67 feb 28, 2014 117 p60 cs0# 118 vcc 119 pd7 d7[a7/d7] mtic5u/poe0# mmc_d1-b/ sdhi_d1-b/ qio1-b/qmi-b irq7 an107 120 pd6 d6[a6/d6] mtic5v/mtioc8a/ poe4# mmc_d0-b/ sdhi_d0-b/ qio0-b/qmo- b irq6 an106 121 pd5 d5[a5/d5] mtic5w/mtioc8c/ poe10# mmc_clk-b/ sdhi_clk-b/ qspclk-b irq5 an113 122 pd4 d4[a4/d4] mtioc8b/poe11# mmc_cmd-b/ sdhi_cmd-b/ qssl-b irq4 an112 123 pd3 d3[a3/d3] mtioc8d/ gtioc0a-e/poe8#/ toc2 mmc_d3-b/ sdhi_d3-b/ qio3-b irq3 an111 124 pd2 d2[a2/d2] mtioc4d/ gtioc0b-e/tic2 crx0 mmc_d2-b/ sdhi_d2-b/ qio2-b irq2 an110 125 pd1 d1[a1/d1] mtioc4b/ gtioc1a-e/poe0# ctx0 irq1 an109 126 pd0 d0[a0/d0] gtioc1b-e/poe4# irq0 an108 127 p93 a19 poe0# cts7#/rts7#/ss7# an117 128 p92 a18 poe4# rxd7/smiso7/sscl7 an116 129 p91 a17 sck7 an115 130 vss 131 p90 a16 txd7/smosi7/ssda7 an114 132 vcc 133 p47 irq15- ds an007 134 p46 irq14- ds an006 135 p45 irq13- ds an005 136 p44 irq12- ds an004 137 p43 irq11-ds an003 138 p42 irq10- ds an002 139 p41 irq9-ds an001 140 vrefl0 141 p40 irq8-ds an000 142 vrefh0 143 avcc0 144 p07 irq15 adtrg0# table 1.8 list of pin and pin functions (144-pin lqfp) (5/5) pin number power supply clock system control i/o port bus exdmac sdramc timer communication memory interface camera interface interrupt s12adc, r12da 144-pin lqfp (mtu, gpta, tpu, tmr, ppg, rtc, cmtw, poe, cac) (etherc, scig, scih, rspi, riic, can, usb, ssi) (qspi, sdhi, mmcif, pdc)
rx64m group 1. overview under development preliminary document specifications in this document are tentative and subject to change. r01ds0173ej0090 rev.0.90 page 57 of 67 feb 28, 2014 table 1.9 list of pin and pin functions (100-pin tflga) (1/4) pin number power supply clock system control i/o port bus exdmac sdramc timer communication memory interface camera interface interrupt s12adc, r12da 100-pin tflga (mtu, gpta, tpu, tmr, ppg, rtc, cmtw, poe, cac) (etherc, scig, scih, rspi, riic, can, usb, ssi) (qspi, sdhi, mmcif, pdc) a1 p05 irq13 da1 a2 avcc1 a3 p07 irq15 adtrg0# a4 vrefl0 a5 p43 irq11- ds an003 a6 pd0 d0[a0/d0] gtioc1b-e/poe4# irq0 an108 a7 pd4 d4[a4/d4] mtioc8b/poe11# mmc_cmd-b/ sdhi_cmd-b/ qssl-b irq4 an112 a8 pe0 d8[a8/d8] mtioc3d/gtioc2b- a sck12 mmc_d4-b anex0 a9 pe1 d9[a9/d9] mtioc4c/mtioc3b/ gtioc1b-a/po18 txd12/smosi12/ ssda12/txdx12/ siox12 mmc_d5-b anex1 a10 pe2 d10[a10/ d10] mtioc4a/gtioc0b- a/po23/tic3 rxd12/smiso12/ sscl12/rxdx12 mmc_d6-b irq7-ds an100 b1 emle b2 avss0 b3 avcc0 b4 p40 irq8-ds an000 b5 p44 irq12- ds an004 b6 pd1 d1[a1/d1] mtioc4b/gtioc1a- e/poe0# ctx0 irq1 an109 b7 pd3 d3[a3/d3] mtioc8d/gtioc0a- e/poe8#/toc2 mmc_d3-b/ sdhi_d3-b/ qio3-b irq3 an111 b8 pd6 d6[a6/d6] mtic5v/mtioc8a/ poe4# mmc_d0-b/ sdhi_d0-b/ qio0-b/qmo-b irq6 an106 b9 pd7 d7[a7/d7] mtic5u/poe0# mmc_d1-b/ sdhi_d1-b/ qio1/qmi-b irq7 an107 b10 pe3 d11[a11/ d11] mtioc4b/gtioc2a- a/po26/poe8#/toc3 cts12#/rts12#/ ss12#/et0_erxd3 mmc_d7-b an101 c1 vcl c2 avss1 c3 pj3 edack1 mtioc3c et0_exout/cts6#/ rts6#/cts0#/rts0#/ ss6#/ss0# c4 vrefh0 c5 p42 irq10- ds an002 c6 p47 irq15- ds an007 c7 pd2 d2[a2/d2] mtioc4d/gtioc0b- e/tic2 crx0 mmc_d2-b/ sdhi_d2-b/ qio2-b irq2 an110
rx64m group 1. overview under development preliminary document specifications in this document are tentative and subject to change. r01ds0173ej0090 rev.0.90 page 58 of 67 feb 28, 2014 c8 pd5 d5[a5/d5] mtic5w/mtioc8c/ poe10# mmc_clk-b/ sdhi_clk-b/ qspclk-b irq5 an113 c9 pe5 d13[a13/ d13] mtioc4c/mtioc2b/ gtioc0a-a et0_rx_clk/ ref50ck0 irq5 an103 c10 pe4 d12[a12/ d12] mtioc4d/mtioc1a/ gtioc1a-a/po28 et0_erxd2 an102 d1 xcin d2 xcout d3 md/fined d4 vbatt d5 p45 irq13- ds an005 d6 p46 irq14- ds an006 d7 pe6 d14[a14/ d14] tioc6c/gtioc3b-e/ tic1 mmc_cd-b/ sdhi_cd-b irq6 an104 d8 pe7 d15[a15/ d15] mtioc6a/gtioc3a- e/toc1 mmc_res#-b/ sdhi_wp-b irq7 an105 d9 pa1 a1 mtioc0b/mtclkc/ mtioc7b/gtioc2a- c/tiocb0/po17 sck5/ssla2-b/ et0_wol irq11 d10 pa0 a0/bc0# mtioc4a/mtioc6d/ gtioc0b-c/tioca0/ cacref/po16 ssla1-b/ et0_tx_en/ rmii0_txd_en e1 xtal p37 e2 vss e3 res# e4 trst# p34 mtioc0a/tmci3/ po12/poe10# sck6/sck0/ et0_linksta irq4 e5 p41 irq9-ds an001 e6 pa2 a2 mtioc7a/gtioc1a- c/po18 rxd5/smiso5/ sscl5/ssla3-b e7 pa6 a6 mtic5v/mtclkb/ gtetrg-c/tioca2/ tmci3/po22/poe10# cts5#/rts5#/ss5#/ mosia-b/ et0_exout e8 pa4 a4 mtic5u/mtclka/ tioca1/tmri0/po20 txd5/smosi5/ ssda5/ssla0-b/ et0_mdc irq5-ds e9 pa5 a5 mtioc6b/tiocb1/ gtioc0a-c/po21 rspcka-b/ et0_linksta e10 pa3 a3 mtioc0d/mtclkd/ tiocd0/tclkb/po19 rxd5/smiso5/ sscl5/et0_mdio irq6-ds f1 extal p36 f2 vcc f3 upsel p35 nmi f4 p32 mtioc0c/tiocc0/ tmo3/po10/ rtcout/rtcic2/ poe0#/poe10# txd6/txd0/smosi6/ smosi0/ssda6/ ssda0/ctx0/ usb0_vbusen irq2-ds f5 p12 tmci1 rxd2/smiso2/ sscl2/scl0[fm+] irq2 table 1.9 list of pin and pin functions (100-pin tflga) (2/4) pin number power supply clock system control i/o port bus exdmac sdramc timer communication memory interface camera interface interrupt s12adc, r12da 100-pin tflga (mtu, gpta, tpu, tmr, ppg, rtc, cmtw, poe, cac) (etherc, scig, scih, rspi, riic, can, usb, ssi) (qspi, sdhi, mmcif, pdc)
rx64m group 1. overview under development preliminary document specifications in this document are tentative and subject to change. r01ds0173ej0090 rev.0.90 page 59 of 67 feb 28, 2014 f6 pb3 a11 mtioc0a/mtioc4a/ tiocd3/tclkd/ tmo0/po27/poe11# sck6/et0_rx_er/ rmii0_rx_er f7 pb2 a10 tiocc3/tclkc/ po26 cts6#/rts6#ss6#/ et0_rx_clk/ ref50ck0 f8 pb0 a8 mtic5w/tioca3/ po24 rxd6/smiso6/ sscl6/et0_erxd1/ rmii0_rxd1 irq12 f9 pa7 a7 tiocb2/po23 misoa-a/et0_wol f10 vss g1 p33 edreq1 mtioc0d/tiocd0/ tmri3/po11/poe4#/ poe11# rxd6/rxd0/smiso6/ smiso0/sscl6/ sscl0/crx0 irq3-ds g2 tms p31 mtioc4d/tmci2/ po9/rtcic1 cts1#/rts1#/ss1# irq1-ds g3 tdi p30 mtioc4b/tmri3/ po8/rtcic0/poe8# rxd1/smiso1/sscl1 irq0-ds g4 tck/finec p27 cs7# mt ioc2b/tmci3/po7 sck1 g5 p53 bclk g6 p52 rd# rxd2/smiso2/sscl2 g7 pb5 a13 mtioc2a/mtioc1b/ tiocb4/tmri1/po29/ poe4# sck9/rts9#/ et0_etxd0/ rmii0_txd0 g8 pb4 a12 tioca4/po28 cts9#/et0_tx_en/ rmii0_txd_en g9 pb1 a9 mtioc0c/mtioc4c/ tiocb3/tmci0/po25 txd6/smosi6/ ssda6/et0_erxd0/ rmii0_rxd0 irq4-ds g10 vcc h1 tdo p26 cs6# mtioc2a/tmo1/po6 txd1/cts3#/rts3#/ smosi1/ss3#/ssda1 h2 p25 cs5#/ edack1 mtioc4c/mtclkb/ tioca4/po5 rxd3/smiso3/ sscl3/ssidata1 adtrg0# h3 p16 mtioc3c/mtioc3d/ tiocb1/tclkc/ tmo2/po14/ rtcout txd1/rxd3/smosi1/ smiso3/ssda1/ sscl3/scl2-ds/ usb0_vbus/ usb0_vbusen/ usb0_ovrcurb irq6 adtrg0# h4 p15 mtioc0b/mtclkb/ gtetrg-b/tiocb2/ tclkb/tmci2/po13 rxd1/sck3/smiso1/ sscl1/crx1-ds/ ssiws1 irq5 h5 p55 wait#/ edreq0 mtioc4d/tmo3 crx1/et0_exout irq10 h6 p54 ale/ edack0 mtioc4b/tmci1 cts2#/rts2#/ss2#/ ctx1/et0_linksta h7 ub pc7 a23/cs0# mtioc3a/mtclkb/ gtioc3a-d/tmo2/ toc0/po31/cacref txd8/misoa-a/ et0_col irq14 h8 pc6 a22/cs1# mtioc3c/mtclka/ gtioc3b-d/tmci2/ tic0/po30 rxd8/mosia-a/ et0_etxd3 irq13 table 1.9 list of pin and pin functions (100-pin tflga) (3/4) pin number power supply clock system control i/o port bus exdmac sdramc timer communication memory interface camera interface interrupt s12adc, r12da 100-pin tflga (mtu, gpta, tpu, tmr, ppg, rtc, cmtw, poe, cac) (etherc, scig, scih, rspi, riic, can, usb, ssi) (qspi, sdhi, mmcif, pdc)
rx64m group 1. overview under development preliminary document specifications in this document are tentative and subject to change. r01ds0173ej0090 rev.0.90 page 60 of 67 feb 28, 2014 h9 pb6 a14 mtioc3d/tioca5/ po30 rxd9/et0_etxd1/ rmii0_txd1 h10 pb7 a15 mtioc3b/tiocb5/ po31 txd9/et0_crs/ rmii0_crs_dv j1 p24 cs4#/ edreq1 mtioc4a/mtclka/ tiocb4/tmri1/po4 sck3/ usb0_vbusen/ ssisck1 j2 p21 mtioc1b/mtioc4a/ gtioc2a-b/tioca3/ tmci0/po1 rxd0/smiso0/ sscl0/ usb0_exicen/ ssiws0 irq9 j3 p17 mtioc3a/mtioc3b/ mtioc4b/gtioc0b- b/tiocb0/tclkd/ tmo1/po15/poe8# sck1/txd3/smosi3/ ssda3/sda2-ds/ ssitxd0 irq7 adtrg1# j4 p13 mtioc0b/tioca5/ tmo3/po13 txd2/smosi2/ ssda2/sda0[fm+] irq3 adtrg1# j5 vss_usb j6 vcc_usb j7 p50 wr0#/wr# txd2/smosi2/ssda2 j8 pc4 a20/cs3# mtioc3d/mtclkc/ gtetrg-d/tmci1/ po25/poe0# sck5/cts8#/ssla0- a/et0_tx_clk j9 pc0 a16 mtioc3c/tclkc/ po17 cts5#/rts5#/ss5#/ ssla1-a/et0_erxd3 irq14 j10 pc1 a17 mtioc3a/tclkd/ po18 sck5/ssla2-a/ et0_erxd2 irq12 k1 p23 edack0 mtioc3d/mtclkd/ gtioc0a-b/tiocd3/ po3 txd3/cts0#/rts0#/ smosi3/ss0#/ ssda3/ssisck0 k2 p22 edreq0 mtioc3b/mtclkc/ gtioc1a-b/tiocc3/ tmo0/po2 sck0/ usb0_ovrcurb/ audio_mclk k3 p20 mtioc1a/tiocb3/ tmri0/po0 txd0/smosi0/ ssda0/usb0_id/ ssirxd0 irq8 k4 p14 mtioc3a/mtclka/ tiocb5/tclka/ tmri2/po15 cts1#/rts1#/ss1#/ ctx1/ usb0_ovrcura irq4 k5 usb0_dm k6 usb0_dp k7 p51 wr1#/bc1#/ wait# sck2 k8 pc5 a21/cs2#/ wait# mtioc3b/mtclkd/ gtioc1a-d/tmri2/ po29 sck8/rspcka-a/ rts8#/et0_etxd2 k9 pc3 a19 mtioc4d/gtioc1b- d/tclkb/po24 txd5/smosi5/ ssda5/et0_tx_er k10 pc2 a18 mtioc4b/gtioc2b- d/tclka/po21 rxd5/smiso5/ sscl5/ssla3-a/ et0_rx_dv table 1.9 list of pin and pin functions (100-pin tflga) (4/4) pin number power supply clock system control i/o port bus exdmac sdramc timer communication memory interface camera interface interrupt s12adc, r12da 100-pin tflga (mtu, gpta, tpu, tmr, ppg, rtc, cmtw, poe, cac) (etherc, scig, scih, rspi, riic, can, usb, ssi) (qspi, sdhi, mmcif, pdc)
rx64m group 1. overview under development preliminary document specifications in this document are tentative and subject to change. r01ds0173ej0090 rev.0.90 page 61 of 67 feb 28, 2014 table 1.10 list of pin and pin functions (100-pin lqfp) (1/4) pin number power supply clock system contro i/o port bus exdmac timer communication memory interface camera interface interrupt s12adc, r12da 100-pin lqfp (mtu, gpta, tpu, tmr, ppg, rtc, cmtw, poe, cac) (etherc, scig, scih, rspi, riic, can, usb, ssi) (qspi, sdhi, mmcif, pdc) 1 avcc1 2emle 3 avss1 4 pj3 edack1 mtioc3c et0_exout cts6#/rts6#/cts0#/ rts0#/ss6#/ss0# 5vcl 6vbatt 7 md/fined 8xcin 9xcout 10 res# 11 xtal p37 12 vss 13 extal p36 14 vcc 15 upsel p35 nmi 16 trst# p34 mtioc0a/tmci3/ po12/poe10# sck6/sck0/ et0_linksta irq4 17 p33 edreq1 mtioc0d/tiocd0/ tmri3/po11/poe4#/ poe11# rxd6/rxd0/smiso6/ smiso0/sscl6/ sscl0/crx0 irq3-ds 18 p32 mtioc0c/tiocc0/ tmo3/po10/ rtcout/rtcic2/ poe0#/poe10# txd6/txd0/smosi6/ smosi0/ssda6/ ssda0/ctx0/ usb0_vbusen irq2-ds 19 tms p31 mtioc4d/tmci2/ po9/rtcic1 cts1#/rts1#/ss1# irq1-ds 20 tdi p30 mtioc4b/tmri3/ po8/rtcic0/poe8# rxd1/smiso1/sscl1 irq0-ds 21 tck/finec p27 cs7# mtioc2b/tmci3/po7 sck1 22 tdo p26 cs6# mtioc2a/tmo1/po6 txd1/cts3#/rts3#/ smosi1/ss3#/ssda1 23 p25 cs5#/ edack1 mtioc4c/mtclkb/ tioca4/po5 rxd3/smiso3/ sscl3/ssidata1 adtrg0# 24 p24 cs4#/ edreq1 mtioc4a/mtclka/ tiocb4/tmri1/po4 sck3/ usb0_vbusen/ ssisck1 25 p23 edack0 mtioc3d/mtclkd/ gtioc0a-b/tiocd3/ po3 txd3/cts0#/rts0#/ smosi3/ss0#/ ssda3/ssisck0 26 p22 edreq0 mtioc3b/mtclkc/ gtioc1a-b/tiocc3/ tmo0/po2 sck0/ usb0_ovrcurb/ audio_mclk 27 p21 mtioc1b/mtioc4a/ gtioc2a-b/tioca3/ tmci0/po1 rxd0/smiso0/ sscl0/ usb0_exicen/ ssiws0 irq9 28 p20 mtioc1a/tiocb3/ tmri0/po0 txd0/smosi0/ ssda0/usb0_id/ ssirxd0 irq8 29 p17 mtioc3a/mtioc3b/ mtioc4b/ gtioc0b-b/tiocb0/ tclkd/tmo1/po15/ poe8# sck1/txd3/smosi3/ ssda3/sda2-ds/ ssitxd0 irq7 adtrg1#
rx64m group 1. overview under development preliminary document specifications in this document are tentative and subject to change. r01ds0173ej0090 rev.0.90 page 62 of 67 feb 28, 2014 30 p16 mtioc3c/mtioc3d/ tiocb1/tclkc/ tmo2/po14/ rtcout txd1/rxd3/smosi1/ smiso3/ssda1/ sscl3/scl2-ds/ usb0_vbus/ usb0_vbusen/ usb0_ovrcurb irq6 adtrg0# 31 p15 mtioc0b/mtclkb/ gtetrg-b/tiocb2/ tclkb/tmci2/po13 rxd1/sck3/smiso1/ sscl1/crx1-ds/ ssiws1 irq5 32 p14 mtioc3a/mtclka/ tiocb5/tclka/ tmri2/po15 cts1#/rts1#/ss1#/ ctx1/ usb0_ovrcura irq4 33 p13 mtioc0b/tioca5/ tmo3/po13 txd2/smosi2/ ssda2/sda0[fm+] irq3 adtrg1# 34 p12 tmci1 rxd2/smiso2/ sscl2/scl0[fm+] irq2 35 vcc_usb 36 usb0_dm 37 usb0_dp 38 vss_usb 39 p55 wait#/ edreq0 mtioc4d/tmo3 crx1/et0_exout irq10 40 p54 ale/edack0 mtioc4b/tmci1 cts2#/rts2#/ss2#/ ctx1/et0_linksta 41 p53 bclk 42 p52 rd# rxd2/smiso2/sscl2 43 p51 wr1#/bc1#/ wait# sck2 44 p50 wr0#/wr# txd2/smosi2/ssda2 45 ub pc7 a23/cs0# mtioc3a/mtclkb/ gtioc3a-d/tmo2/ toc0/po31/cacref txd8/misoa-a/ et0_col irq14 46 pc6 a22/cs1# mtioc3c/mtclka/ gtioc3b-d/tmci2/ tic0/po30 rxd8/mosia-a/ et0_etxd3 irq13 47 pc5 a21/cs2#/ wait# mtioc3b/mtclkd/ gtioc1a-d/tmri2/ po29 sck8/rspcka-a/ rts8#/et0_etxd2 48 pc4 a20/cs3# mtioc3d/mtclkc/ gtetrg-d/tmci1/ po25/poe0# sck5/cts8#/ ssla0-a/ et0_tx_clk 49 pc3 a19 mtioc4d/ gtioc1b-d/tclkb/ po24 txd5/smosi5/ ssda5/et0_tx_er 50 pc2 a18 mtioc4b/ gtioc2b-d/tclka/ po21 rxd5/smiso5/ sscl5/ssla3-a/ et0_rx_dv 51 pc1 a17 mtioc3a/tclkd/ po18 sck5/ssla2-a/ et0_erxd2 irq12 52 pc0 a16 mtioc3c/tclkc/ po17 cts5#/rts5#/ss5#/ ssla1-a/et0_erxd3 irq14 53 pb7 a15 mtioc3b/tiocb5/ po31 txd9/et0_crs/ rmii0_crs_dv 54 pb6 a14 mtioc3d/tioca5/ po30 rxd9/et0_etxd1/ rmii0_txd1 55 pb5 a13 mtioc2a/mtioc1b/ tiocb4/tmri1/po29/ poe4# sck9/rts9#/ et0_etxd0/ rmii0_txd0 56 pb4 a 12 t ioca4/po28 cts9#/et0_tx_en/ rmii0_txd_en table 1.10 list of pin and pin functions (100-pin lqfp) (2/4) pin number power supply clock system contro i/o port bus exdmac timer communication memory interface camera interface interrupt s12adc, r12da 100-pin lqfp (mtu, gpta, tpu, tmr, ppg, rtc, cmtw, poe, cac) (etherc, scig, scih, rspi, riic, can, usb, ssi) (qspi, sdhi, mmcif, pdc)
rx64m group 1. overview under development preliminary document specifications in this document are tentative and subject to change. r01ds0173ej0090 rev.0.90 page 63 of 67 feb 28, 2014 57 pb3 a11 mtioc0a/mtioc4a/ tiocd3/tclkd/ tmo0/po27/poe11# sck6/et0_rx_er/ rmii0_rx_er 58 pb2 a10 tiocc3/tclkc/ po26 cts6#/rts6#ss6#/ et0_rx_clk/ ref50ck0 59 pb1 a9 mtioc0c/mtioc4c/ tiocb3/tmci0/po25 txd6/smosi6/ ssda6/et0_erxd0/ rmii0_rxd0 irq4-ds 60 vcc 61 pb0 a8 mtic5w/tioca3/ po24 rxd6/smiso6/ sscl6/et0_erxd1/ rmii0_rxd1 irq12 62 vss 63 pa7 a7 tiocb2/po23 misoa-a/et0_wol 64 pa6 a6 mtic5v/mtclkb/ gtetrg-c/tioca2/ tmci3/po22/poe10# cts5#/rts5#/ss5#/ mosia-b/ et0_exout 65 pa5 a5 mtioc6b/tiocb1/ gtioc0a-c/po21 rspcka-b/ et0_linksta 66 pa4 a4 mtic5u/mtclka/ tioca1/tmri0/po20 txd5/smosi5/ ssda5/ssla0-b/ et0_mdc irq5-ds 67 pa3 a3 mtioc0d/mtclkd/ tiocd0/tclkb/po19 rxd5/smiso5/ sscl5/et0_mdio irq6-ds 68 pa2 a2 mtioc7a/ gtioc1a-c/po18 rxd5/smiso5/ sscl5/ssla3-b 69 pa1 a1 mtioc0b/mtclkc/ mtioc7b/ gtioc2a-c/tiocb0/ po17 sck5/ssla2-b/ et0_wol irq11 70 pa0 a0/bc0# mtioc4a/mtioc6d/ gtioc0b-c/tioca0/ cacref/po16 ssla1-b/ et0_tx_en/ rmii0_txd_en 71 pe7 d15[a15/d15] mtioc6a/ gtioc3a-e/toc1 mmc_res#-b/ sdhi_wp-b irq7 an105 72 pe6 d14[a14/d14] tioc6c/gtioc3b-e/ tic1 mmc_cd-b/ sdhi_cd-b irq6 an104 73 pe5 d13[a13/d13] mtioc4c/mtioc2b/ gtioc0a-a et0_rx_clk/ ref50ck0 irq5 an103 74 pe4 d12[a12/d12] mtioc4d/mtioc1a/ gtioc1a-a/po28 et0_erxd2 an102 75 pe3 d11[a11/d11] mtioc4b/ gtioc2a-a/po26/ poe8#/toc3 cts12#/rts12#/ ss12#/et0_erxd3 mmc_d7-b an101 76 pe2 d10[a10/d10] mtioc4a/ gtioc0b-a/po23/ tic3 rxd12/smiso12/ sscl12/rxdx12 mmc_d6-b irq7-ds an100 77 pe1 d9[a9/d9] mtioc4c/mtioc3b/ gtioc1b-a/po18 txd12/smosi12/ ssda12/txdx12/ siox12 mmc_d5-b anex1 78 pe0 d8[a8/d8] mtioc3d/ gtioc2b-a sck12 mmc_d4-b anex0 79 pd7 d7[a7/d7] mtic5u/poe0# mmc_d1-b/ sdhi_d1-b/ qio1-b/ qmi-b irq7 an107 80 pd6 d6[a6/d6] mtic5v/mtioc8a/ poe4# mmc_d0- b/ sdhi_d0-b/ qio0- b/ qmo-b irq6 an106 table 1.10 list of pin and pin functions (100-pin lqfp) (3/4) pin number power supply clock system contro i/o port bus exdmac timer communication memory interface camera interface interrupt s12adc, r12da 100-pin lqfp (mtu, gpta, tpu, tmr, ppg, rtc, cmtw, poe, cac) (etherc, scig, scih, rspi, riic, can, usb, ssi) (qspi, sdhi, mmcif, pdc)
rx64m group 1. overview under development preliminary document specifications in this document are tentative and subject to change. r01ds0173ej0090 rev.0.90 page 64 of 67 feb 28, 2014 81 pd5 d5[a5/d5] mtic5w/mtioc8c/ poe10# mmc_clk-b/ sdhi_clk-b/ qspclk-b irq5 an113 82 pd4 d4[a4/d4] mtioc8b/poe11# mmc_cmd-b/ sdhi_cmd-b/ qssl-b irq4 an112 83 pd3 d3[a3/d3] mtioc8d/ gtioc0a-e/poe8#/ toc2 mmc_d3-b/ sdhi_d3-b/ qio3-b irq3 an111 84 pd2 d2[a2/d2] mtioc4d/ gtioc0b-e/tic2 crx0 mmc_d2-b/ sdhi_d2-b/ qio2-b irq2 an110 85 pd1 d1[a1/d1] mtioc4b/ gtioc1a-e/poe0# ctx0 irq1 an109 86 pd0 d0[a0/d0] gtioc1b-e/poe4# irq0 an108 87 p47 irq15-ds an007 88 p46 irq14-ds an006 89 p45 irq13-ds an005 90 p44 irq12-ds an004 91 p43 irq11-ds an003 92 p42 irq10-ds an002 93 p41 irq9-ds an001 94 vrefl0 95 p40 irq8-ds an000 96 vrefh0 97 avcc0 98 p07 irq15 adtrg0# 99 avss0 100 p05 irq13 da1 table 1.10 list of pin and pin functions (100-pin lqfp) (4/4) pin number power supply clock system contro i/o port bus exdmac timer communication memory interface camera interface interrupt s12adc, r12da 100-pin lqfp (mtu, gpta, tpu, tmr, ppg, rtc, cmtw, poe, cac) (etherc, scig, scih, rspi, riic, can, usb, ssi) (qspi, sdhi, mmcif, pdc)
r01ds0173ej0090 rev.0.90 page 65 of 67 feb 28, 2014 rx64m group revision history under development preliminary document specifications in this document are tentative and subject to change. revision history rx64m group datasheet rev. date description page summary 0.90 feb 28, 2014 ? first edition, issued all trademarks and registered trademarks are the property of thei r respective owners. revision history
general precautions in the handling of mpu/mcu products the following usage notes are applicable to all mpu/mcu pr oducts from renesas. for detailed usage notes on the products covered by this document, refer to the relevant sections of the document as well as any technical updates that have been issued for the products. 1. handling of unused pins handle unused pins in accordance with the dire ctions given under handling of unused pins in the manual. ? the input pins of cmos products are generally in the high-impedance state. in operation with an unused pin in the open-circuit state, extra electromag netic noise is induced in the vicinity of lsi, an associated shoot-through current flows internally, and malfunctions occur due to the false recognition of the pin state as an input signal be come possible. unused pins should be handled as described under handling of unused pins in the manual. 2. processing at power-on the state of the product is undefined at the moment when power is supplied. ? the states of internal circuits in the lsi are indeterminate and the states of register settings and pins are undefined at the moment when power is supplied. in a finished product where the reset signal is applie d to the external reset pin, the states of pins are not guaranteed from the moment when power is supplied until the reset pr ocess is completed. in a similar way, the states of pins in a product that is reset by an on-chip power-on reset function are not guaranteed from the moment when power is supplied until the power reaches the level at which resetting has been specified. 3. prohibition of access to reserved addresses access to reserved addresses is prohibited. ? the reserved addresses are provid ed for the possible future expansi on of functions. do not access these addresses; the correct operation of ls i is not guaranteed if they are accessed. 4. clock signals after applying a reset, only release the reset line after the operating clock signal has become stable. when switching the clock signal during program ex ecution, wait until the target clock signal has stabilized. ? when the clock signal is gene rated with an external resonator (or from an external oscillator) during a reset, ensure that the reset line is only re leased after full stabilization of the clock signal. moreover, when switching to a clock signal produc ed with an external resonator (or by an external oscillator) while program ex ecution is in progress, wait until t he target clock signal is stable. 5. differences between products before changing from one product to another, i.e. to a product with a different part number, confirm that the change will not lead to problems. ? the characteristics of an mpu or mcu in the same group but having a different part number may differ in terms of the internal memory capacity, layout pattern, and other factors, which can affect the ranges of electrical characteristics, such as characteristic values, ope rating margins, immunity to noise, and amount of radiated noise. when changing to a product with a different part number, implement a system-evaluation test for the given product.
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"standard": computers; office equipment; communications equipment; test and measurement equipment; audio and visual equipment; home electronic appliances; machine tools; personal electronic equipment; and industrial robots etc. "high quality": transportation equipment (automobiles, trains, ships, etc.); traffic control systems; anti-disaster systems; an ti-crime systems; and safety equipment etc. renesas electronics products are neither intended nor authorized for use in products or systems that may pose a direct threat t o human life or bodily injury (artificial life support devices or systems, surgical implantations etc.), or may cause serious property damages (nuclear reactor control systems, military equipment etc.). you mus t check the quality grade of each renesas electronics product before using it in a particular application. you may not use any renesas electronics product for any application for which it is not intended. renesas electronics shall not be in any way liable for any damages or losses incurred by you or third parties arising from the use of any renesas electronics product for which the product is not intended by renesas electronics. 6. you should use the renesas electronics products described in this document within the range specified by renesas electronics , especially with respect to the maximum rating, operating supply voltage range, movement power voltage range, heat radiation characteristics, installation and other product characteristics. renesas e lectronics shall have no liability for malfunctions or damages arising out of the use of renesas electronics products beyond such specified ranges. 7. although renesas electronics endeavors to improve the quality and reliability of its products, semiconductor products have s pecific characteristics such as the occurrence of failure at a certain rate and malfunctions under certain use conditions. further, renesas electronics products are not subject to radiation resistance desig n. please be sure to implement safety measures to guard them against the possibility of physical injury, and injury or damage caused by fire in the event of the failure of a renesas electronics produc t, such as safety design for hardware and software including but not limited to redundancy, fire control and malfunction prevention, appropriate treatment for aging degradation or any other appropriate measu res. because the evaluation of microcomputer software alone is very difficult, please evaluate the safety of the final products or systems manufactured by you. 8. please contact a renesas electronics sales office for details as to environmental matters such as the environmental compatib ility of each renesas electronics product. please use renesas electronics products in compliance with all applicable laws and regulations that regulate the inclusion or use of controlled substances, in cluding without limitation, the eu rohs directive. renesas electronics assumes no liability for damages or losses occurring as a result of your noncompliance with applicable laws and regulations. 9. renesas electronics products and technology may not be used for or incorporated into any products or systems whose manufactu re, use, or sale is prohibited under any applicable domestic or foreign laws or regulations. you should not use renesas electronics products or technology described in this document for any purpose relating to military applications or use by the military, including but not limited to the development of weapons of mass destruction. when exporting the renesas electronics products or technology described in this do cument, you should comply with the applicable export control laws and regulations and follow the procedures required by such laws and regulations. 10. it is the responsibility of the buyer or distributor of renesas electronics products, who distributes, disposes of, or othe rwise places the product with a third party, to notify such third party in advance of the contents and conditions set forth in this document, renesas electronics assumes no responsibility for any losses incurred by yo u or third parties as a result of unauthorized use of renesas electronics products. 11. this document may not be reproduced or duplicated in any form, in whole or in part, without prior written consent of renesa s electronics. 12. please contact a renesas electronics sales office if you have any questions regarding the information contained in this doc ument or renesas electronics products, or if you have any other inquiries. (note 1) "renesas electronics" as used in this document means renesas electronics corporation and also includes its majority-o wned subsidiaries. (note 2) "renesas electronics product(s)" means any product developed or manufactured by or for renesas electronics. http://www.renesas.com refer to "http://www.renesas.com/" for the latest and detailed information. renesas electronics america inc. 2801 scott boulevard santa clara, ca 95050-2549, u.s.a. tel: +1-408-588-6000, fax: +1-408-588-6130 renesas electronics canada limited 1101 nicholson road, newmarket, ontario l3y 9c3, canada tel: +1-905-898-5441, fax: +1-905-898-3220 renesas electronics europe limited dukes meadow, millboard road, bourne end, buckinghamshire, sl8 5fh, u.k tel: +44-1628-585-100, fax: +44-1628-585-900 renesas electronics europe gmbh arcadiastrasse 10, 40472 dsseldorf, germany tel: +49-211-6503-0, fax: +49-211-6503-1327 renesas electronics (china) co., ltd. room 1709, quantum plaza, no.27 zhichunlu haidian district, beijing 100191, p.r.china tel: +86-10-8235-1155, fax: +86-10-8235-7679 renesas electronics (shanghai) co., ltd. unit 301, tower a, central towers, 555 langao road, putuo district, shanghai, p. r. china 200333 tel: +86-21-2226-0888, fax: +86-21-2226-0999 renesas electronics hong kong limited unit 1601-1613, 16/f., tower 2, grand century place, 193 prince edward road west, mongkok, kowloon, hong kong tel: +852-2265-6688, fax: +852 2886-9022/9044 renesas electronics taiwan co., ltd. 13f, no. 363, fu shing north road, taipei 10543, taiwan tel: +886-2-8175-9600, fax: +886 2-8175-9670 renesas electronics singapore pte. ltd. 80 bendemeer road, unit #06-02 hyflux innovation centre, singapore 339949 tel: +65-6213-0200, fax: +65-6213-0300 renesas electronics malaysia sdn.bhd. unit 906, block b, menara amcorp, amcorp trade centre, no. 18, jln persiaran barat, 46050 petaling jaya, selangor darul ehsan, malaysia tel: +60-3-7955-9390, fax: +60-3-7955-9510 renesas electronics korea co., ltd. 12f., 234 teheran-ro, gangnam-ku, seoul, 135-920, korea tel: +82-2-558-3737, fax: +82-2-558-5141 sales offices ? 2014 renesas electronics corporation. all rights reserved. colophon 4.0

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